dev/irq/arm-gic-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This header file provides interfaces of the ARM Generic Interrupt
0009  *   Controller (GIC) memory-mapped registers.
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
0038 #define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
0039
0040 #include <bsp/utility.h>
0041
0042 /**
0043  * @addtogroup DevIRQGIC
0044  *
0045  * @{
0046  */
0047
0048 typedef struct {
0049   uint32_t iccicr;
0050 #define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
0051 #define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
0052 #define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
0053 #define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
0054 #define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
0055   uint32_t iccpmr;
0056 #define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
0057 #define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
0058 #define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0059   uint32_t iccbpr;
0060 #define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
0061 #define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
0062 #define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
0063   uint32_t icciar;
0064 #define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
0065 #define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
0066 #define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
0067 #define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
0068 #define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
0069 #define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0070   uint32_t icceoir;
0071 #define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
0072 #define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
0073 #define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
0074 #define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
0075 #define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
0076 #define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0077   uint32_t iccrpr;
0078 #define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
0079 #define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
0080 #define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0081   uint32_t icchpir;
0082 #define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
0083 #define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
0084 #define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
0085 #define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
0086 #define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
0087 #define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0088   uint32_t iccabpr;
0089 #define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
0090 #define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
0091 #define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
0092   uint32_t reserved_20[55];
0093   uint32_t icciidr;
0094 #define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
0095 #define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
0096 #define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
0097 #define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
0098 #define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
0099 #define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
0100 #define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
0101 #define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
0102 #define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
0103 #define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
0104 #define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
0105 #define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
0106 } gic_cpuif;
0107
0108 typedef struct {
0109   /* GICD_CTLR */
0110   uint32_t icddcr;
0111 /* GICv3 only */
0112 #define GIC_DIST_ICDDCR_RWP BSP_BIT32(31)
0113 #define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7)
0114 #define GIC_DIST_ICDDCR_DS BSP_BIT32(6)
0115 #define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5)
0116 #define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4)
0117 #define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2)
0118 #define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1)
0119 #define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0)
0120 /* GICv1/GICv2 */
0121 #define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
0122 #define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
0123   uint32_t icdictr;
0124 #define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
0125 #define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
0126 #define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
0127 #define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
0128 #define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
0129 #define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
0130 #define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
0131 #define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
0132 #define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
0133 #define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0134   uint32_t icdiidr;
0135 #define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
0136 #define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
0137 #define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
0138 #define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
0139 #define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
0140 #define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
0141 #define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
0142 #define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
0143 #define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
0144 #define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
0145 #define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
0146 #define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
0147   uint32_t gicd_typer2;
0148   uint32_t gicd_statusr;
0149   uint32_t reserved_14[11];
0150   uint32_t gicd_setspi_nsr;
0151   uint32_t reserved_44[1];
0152   uint32_t gicd_clrspi_nsr;
0153   uint32_t reserved_4c[1];
0154   uint32_t gicd_setspi_sr;
0155   uint32_t reserved_54[1];
0156   uint32_t gicd_clrspi_sr;
0157   uint32_t reserved_5c[9];
0158   uint32_t icdigr[32];
0159   uint32_t icdiser[32];
0160   uint32_t icdicer[32];
0161   uint32_t icdispr[32];
0162   uint32_t icdicpr[32];
0163   uint32_t icdabr[32];
0164   uint32_t gicd_icactiver[32];
0165   uint8_t icdipr[1024];
0166   uint8_t icdiptr[1024];
0167   uint32_t icdicfr[64];
0168   /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */
0169   uint32_t icdigmr[32];
0170   uint32_t reserved_d80[32];
0171   uint32_t gicd_nsacr[64];
0172   uint32_t icdsgir;
0173 #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
0174 #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
0175 #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
0176 #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
0177 #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
0178 #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
0179 #define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15)
0180 #define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
0181 #define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
0182 #define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
0183   uint32_t reserved_f04[3];
0184   uint32_t gicd_cpendsgir[4];
0185   uint32_t gicd_spendsgir[4];
0186   uint32_t reserved_f80[20];
0187   uint32_t gicd_inmir[32];
0188   uint32_t gicd_igroupre[32];
0189   uint32_t reserved_1080[96];
0190   uint32_t gicd_isenablere[32];
0191   uint32_t reserved_1280[96];
0192   uint32_t gicd_icenablere[32];
0193   uint32_t reserved_1480[96];
0194   uint32_t gicd_ispendre[32];
0195   uint32_t reserved_1680[96];
0196   uint32_t gicd_icpendre[32];
0197   uint32_t reserved_1880[96];
0198   uint32_t gicd_isactivere[32];
0199   uint32_t reserved_1a80[96];
0200   uint32_t gicd_icactivere[32];
0201   uint32_t reserved_1c80[224];
0202   uint8_t gicd_ipriorityre[1024];
0203   uint32_t reserved_2400[768];
0204   uint32_t gicd_icfgre[64];
0205   uint32_t reserved_3100[192];
0206   uint32_t gicd_igrpmodre[32];
0207   uint32_t reserved_3480[96];
0208   uint32_t gicd_nsacre[32];
0209   uint32_t reserved_3680[288];
0210   uint32_t gicd_inmire[32];
0211   uint32_t reserved_3b80[2400];
0212   uint64_t gicd_irouter[992];
0213   uint64_t gicd_iroutere[4096];
0214 } gic_dist;
0215
0216 /* GICv3 only */
0217 typedef struct {
0218   /* GICR_CTLR */
0219   uint32_t icrrcr;
0220 #define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31)
0221 #define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26)
0222 #define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25)
0223 #define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24)
0224 #define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4)
0225 #define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0)
0226   uint32_t icriidr;
0227   uint64_t icrtyper;
0228 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63)
0229 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63)
0230 #define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63)
0231 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25)
0232 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25)
0233 #define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25)
0234 #define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23)
0235 #define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23)
0236 #define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23)
0237 #define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5)
0238 #define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4)
0239 #define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3)
0240 #define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1)
0241 #define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0)
0242   uint32_t unused_10;
0243   uint32_t icrwaker;
0244 #define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2)
0245 #define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1)
0246 } gic_redist;
0247
0248 /* GICv3 only */
0249 typedef struct {
0250   uint32_t reserved_0_80[32];
0251   /* GICR_IGROUPR0 */
0252   uint32_t icspigrpr[32];
0253   /* GICR_ISENABLER0 */
0254   uint32_t icspiser[32];
0255   /* GICR_ICENABLER0 */
0256   uint32_t icspicer[32];
0257   /* GICR_ISPENDR0 */
0258   uint32_t icspispendr[32];
0259   /* GICR_ICPENDR0 */
0260   uint32_t icspicpendr[32];
0261   /* GICR_ISACTIVER0 */
0262   uint32_t icspisar[32];
0263   /* GICR_ICACTIVER0 */
0264   uint32_t icspicar[32];
0265   /* GICR_IPRIORITYR */
0266   uint8_t icspiprior[32];
0267   uint32_t reserved_420_bfc[504];
0268   /* GICR_ICFGR0 and GICR_ICFGR1 */
0269   uint32_t icspicfgr[2];
0270   uint32_t reserved_c08_cfc[62];
0271   /* GICR_IGRPMODR0 */
0272   uint32_t icspigrpmodr[64];
0273 } gic_sgi_ppi;
0274
0275 /** @} */
0276
0277 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */