dev/irq/arm-gic-irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This header file provides interfaces of the ARM Generic Interrupt
0009  *   Controller (GIC) support.
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
0038 #define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
0039
0040 #include <bsp.h>
0041 #include <dev/irq/arm-gic.h>
0042
0043 #ifdef __cplusplus
0044 extern "C" {
0045 #endif /* __cplusplus */
0046
0047 /**
0048  * @addtogroup DevIRQGIC
0049  *
0050  * @{
0051  */
0052
0053 #define ARM_GIC_IRQ_SGI_0 0
0054 #define ARM_GIC_IRQ_SGI_1 1
0055 #define ARM_GIC_IRQ_SGI_2 2
0056 #define ARM_GIC_IRQ_SGI_3 3
0057 #define ARM_GIC_IRQ_SGI_5 5
0058 #define ARM_GIC_IRQ_SGI_6 6
0059 #define ARM_GIC_IRQ_SGI_7 7
0060 #define ARM_GIC_IRQ_SGI_8 8
0061 #define ARM_GIC_IRQ_SGI_9 9
0062 #define ARM_GIC_IRQ_SGI_10 10
0063 #define ARM_GIC_IRQ_SGI_11 11
0064 #define ARM_GIC_IRQ_SGI_12 12
0065 #define ARM_GIC_IRQ_SGI_13 13
0066 #define ARM_GIC_IRQ_SGI_14 14
0067 #define ARM_GIC_IRQ_SGI_15 15
0068 #define ARM_GIC_IRQ_SGI_LAST 15
0069
0070 #define ARM_GIC_IRQ_PPI_LAST 31
0071
0072 #define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
0073
0074 rtems_status_code arm_gic_irq_set_group(
0075   rtems_vector_number vector,
0076   gic_group group
0077 );
0078
0079 rtems_status_code arm_gic_irq_get_group(
0080   rtems_vector_number vector,
0081   gic_group *group
0082 );
0083
0084 void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
0085
0086 #ifdef RTEMS_SMP
0087 uint32_t arm_gic_irq_processor_count(void);
0088
0089 void arm_gic_irq_initialize_secondary_cpu(void);
0090 #endif
0091
0092 /** @} */
0093
0094 #ifdef __cplusplus
0095 }
0096 #endif /* __cplusplus */
0097
0098 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */