dev/i2c/cadence-i2c-regs.h

0001 /*
0002  * SPDX-License-Identifier: BSD-2-Clause
0003  *
0004  * Copyright (C) 2014 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H
0029 #define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H
0030
0031 #include <bsp/utility.h>
0032
0033 typedef struct {
0034     uint32_t control;
0035 #define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15)
0036 #define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15)
0037 #define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15)
0038 #define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13)
0039 #define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13)
0040 #define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
0041 #define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6)
0042 #define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5)
0043 #define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4)
0044 #define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3)
0045 #define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2)
0046 #define CADENCE_I2C_CONTROL_MS BSP_BIT32(1)
0047 #define CADENCE_I2C_CONTROL_RW BSP_BIT32(0)
0048     uint32_t status;
0049 #define CADENCE_I2C_STATUS_BA BSP_BIT32(8)
0050 #define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7)
0051 #define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6)
0052 #define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5)
0053 #define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3)
0054     uint32_t address;
0055 #define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9)
0056 #define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9)
0057 #define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0058     uint32_t data;
0059     uint32_t irqstatus;
0060 #define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9)
0061 #define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7)
0062 #define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6)
0063 #define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5)
0064 #define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4)
0065 #define CADENCE_I2C_IXR_TO BSP_BIT32(3)
0066 #define CADENCE_I2C_IXR_NACK BSP_BIT32(2)
0067 #define CADENCE_I2C_IXR_DATA BSP_BIT32(1)
0068 #define CADENCE_I2C_IXR_COMP BSP_BIT32(0)
0069     uint32_t transfer_size;
0070 #define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7)
0071 #define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7)
0072 #define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0073     uint32_t slave_mon_pause;
0074 #define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3)
0075 #define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3)
0076 #define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
0077     uint32_t timeout;
0078 #define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7)
0079 #define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7)
0080 #define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0081     uint32_t irqmask;
0082     uint32_t irqenable;
0083     uint32_t irqdisable;
0084 } cadence_i2c;
0085
0086 #endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */