dev/clock/xttcps_hw.h

0001 /******************************************************************************
0002 * Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005
0006 /*****************************************************************************/
0007 /**
0008 *
0009 * @file xttcps_hw.h
0010 * @ingroup RTEMSDriverClockXilTTC
0011 * This file defines the hardware interface to one of the three timer counters
0012 * in the Ps block.
0013 *
0014 *
0015 * <pre>
0016 * MODIFICATION HISTORY:
0017 *
0018 * Ver   Who    Date     Changes
0019 * ----- ------ -------- -------------------------------------------------
0020 * 1.00a drg/jz 01/21/10 First release
0021 * 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
0022 * 3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
0023 *                       XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
0024 *                       mask 16 bit values for zynq and 32 bit values for
0025 *                       zynq ultrascale+mpsoc "
0026 * </pre>
0027 *
0028 * @addtogroup RTEMSDriverClockXilTTC
0029 * @{
0030 ******************************************************************************/
0031
0032 #ifndef XTTCPS_HW_H     /* prevent circular inclusions */
0033 #define XTTCPS_HW_H     /* by using protection macros */
0034
0035 #ifdef __cplusplus
0036 extern "C" {
0037 #endif
0038
0039 /***************************** Include Files *********************************/
0040
0041 #ifndef __rtems__
0042 #include "xil_types.h"
0043 #include "xil_assert.h"
0044 #include "xil_io.h"
0045 #else
0046 #include <bsp/xil-compat.h>
0047 #endif
0048
0049 /************************** Constant Definitions *****************************/
0050 /*
0051  * Flag for a9 processor
0052  */
0053  #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
0054  #define ARMA9
0055  #endif
0056
0057 /** @name Register Map
0058  *
0059  * Register offsets from the base address of the device.
0060  *
0061  * @{
0062  */
0063 #define XTTCPS_CLK_CNTRL_OFFSET     0x00000000U  /**< Clock Control Register */
0064 #define XTTCPS_CNT_CNTRL_OFFSET     0x0000000CU  /**< Counter Control Register*/
0065 #define XTTCPS_COUNT_VALUE_OFFSET   0x00000018U  /**< Current Counter Value */
0066 #define XTTCPS_INTERVAL_VAL_OFFSET  0x00000024U  /**< Interval Count Value */
0067 #define XTTCPS_MATCH_0_OFFSET       0x00000030U  /**< Match 1 value */
0068 #define XTTCPS_MATCH_1_OFFSET       0x0000003CU  /**< Match 2 value */
0069 #define XTTCPS_MATCH_2_OFFSET       0x00000048U  /**< Match 3 value */
0070 #define XTTCPS_ISR_OFFSET           0x00000054U  /**< Interrupt Status Register */
0071 #define XTTCPS_IER_OFFSET           0x00000060U  /**< Interrupt Enable Register */
0072 /* @} */
0073
0074 /** @name Clock Control Register
0075  * Clock Control Register definitions
0076  * @{
0077  */
0078 #define XTTCPS_CLK_CNTRL_PS_EN_MASK     0x00000001U  /**< Prescale enable */
0079 #define XTTCPS_CLK_CNTRL_PS_VAL_MASK    0x0000001EU  /**< Prescale value */
0080 #define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT            1U  /**< Prescale shift */
0081 #define XTTCPS_CLK_CNTRL_PS_DISABLE             16U  /**< Prescale disable */
0082 #define XTTCPS_CLK_CNTRL_SRC_MASK       0x00000020U  /**< Clock source */
0083 #define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK  0x00000040U  /**< External Clock edge */
0084 /* @} */
0085
0086 /** @name Counter Control Register
0087  * Counter Control Register definitions
0088  * @{
0089  */
0090 #define XTTCPS_CNT_CNTRL_DIS_MASK       0x00000001U /**< Disable the counter */
0091 #define XTTCPS_CNT_CNTRL_INT_MASK       0x00000002U /**< Interval mode */
0092 #define XTTCPS_CNT_CNTRL_DECR_MASK      0x00000004U /**< Decrement mode */
0093 #define XTTCPS_CNT_CNTRL_MATCH_MASK     0x00000008U /**< Match mode */
0094 #define XTTCPS_CNT_CNTRL_RST_MASK       0x00000010U /**< Reset counter */
0095 #define XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U /**< Enable waveform */
0096 #define XTTCPS_CNT_CNTRL_POL_WAVE_MASK  0x00000040U /**< Waveform polarity */
0097 #define XTTCPS_CNT_CNTRL_RESET_VALUE    0x00000021U /**< Reset value */
0098 /* @} */
0099
0100 /** @name Current Counter Value Register
0101  * Current Counter Value Register definitions
0102  * @{
0103  */
0104 #if defined(ARMA9)
0105 #define XTTCPS_COUNT_VALUE_MASK     0x0000FFFFU /**< 16-bit counter value */
0106 #else
0107 #define XTTCPS_COUNT_VALUE_MASK     0xFFFFFFFFU /**< 32-bit counter value */
0108 #endif
0109 /* @} */
0110
0111 /** @name Interval Value Register
0112  * Interval Value Register is the maximum value the counter will count up or
0113  * down to.
0114  * @{
0115  */
0116 #if defined(ARMA9)
0117 #define XTTCPS_INTERVAL_VAL_MASK    0x0000FFFFU /**< 16-bit Interval value*/
0118 #else
0119 #define XTTCPS_INTERVAL_VAL_MASK    0xFFFFFFFFU /**< 32-bit Interval value*/
0120 #endif
0121 /* @} */
0122
0123 /** @name Match Registers
0124  * Definitions for Match registers, each timer counter has three match
0125  * registers.
0126  * @{
0127  */
0128 #if defined(ARMA9)
0129 #define XTTCPS_MATCH_MASK       0x0000FFFFU /**< 16-bit Match value */
0130 #else
0131 #define XTTCPS_MATCH_MASK       0xFFFFFFFFU /**< 32-bit Match value */
0132 #endif
0133 #define XTTCPS_NUM_MATCH_REG             3U /**< Num of Match reg */
0134 /* @} */
0135
0136 /** @name Interrupt Registers
0137  * Following register bit mask is for all interrupt registers.
0138  *
0139  * @{
0140  */
0141 #define XTTCPS_IXR_INTERVAL_MASK    0x00000001U  /**< Interval Interrupt */
0142 #define XTTCPS_IXR_MATCH_0_MASK     0x00000002U  /**< Match 1 Interrupt */
0143 #define XTTCPS_IXR_MATCH_1_MASK     0x00000004U  /**< Match 2 Interrupt */
0144 #define XTTCPS_IXR_MATCH_2_MASK     0x00000008U  /**< Match 3 Interrupt */
0145 #define XTTCPS_IXR_CNT_OVR_MASK     0x00000010U  /**< Counter Overflow */
0146 #define XTTCPS_IXR_ALL_MASK         0x0000001FU  /**< All valid Interrupts */
0147 /* @} */
0148
0149
0150 /***************** Macros (Inline Functions) Definitions *********************/
0151
0152 /****************************************************************************/
0153 /**
0154 *
0155 * Read the given Timer Counter register.
0156 *
0157 * @param    BaseAddress is the base address of the timer counter device.
0158 * @param    RegOffset is the register offset to be read
0159 *
0160 * @return   The 32-bit value of the register
0161 *
0162 * @note     C-style signature:
0163 *       u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
0164 *
0165 *****************************************************************************/
0166 #define XTtcPs_ReadReg(BaseAddress, RegOffset) \
0167     (Xil_In32((BaseAddress) + (u32)(RegOffset)))
0168
0169 /****************************************************************************/
0170 /**
0171 *
0172 * Write the given Timer Counter register.
0173 *
0174 * @param    BaseAddress is the base address of the timer counter device.
0175 * @param    RegOffset is the register offset to be written
0176 * @param    Data is the 32-bit value to write to the register
0177 *
0178 * @return   None.
0179 *
0180 * @note     C-style signature:
0181 *       void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
0182 *       u32 Data)
0183 *
0184 *****************************************************************************/
0185 #define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
0186     (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
0187
0188 /****************************************************************************/
0189 /**
0190 *
0191 * Calculate a match register offset using the Match Register index.
0192 *
0193 * @param    MatchIndex is the 0-2 value of the match register
0194 *
0195 * @return   MATCH_N_OFFSET.
0196 *
0197 * @note     C-style signature:
0198 *       u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
0199 *
0200 *****************************************************************************/
0201 #define XTtcPs_Match_N_Offset(MatchIndex) \
0202         ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
0203
0204 /************************** Function Prototypes ******************************/
0205
0206 /************************** Variable Definitions *****************************/
0207 #ifdef __cplusplus
0208 }
0209 #endif
0210 #endif /* end of protection macro */
0211 /** @} */