shared/irq/elcr.c

0001 /*-
0002  * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
0003  * All rights reserved.
0004  *
0005  * Redistribution and use in source and binary forms, with or without
0006  * modification, are permitted provided that the following conditions
0007  * are met:
0008  * 1. Redistributions of source code must retain the above copyright
0009  *    notice, this list of conditions and the following disclaimer.
0010  * 2. Redistributions in binary form must reproduce the above copyright
0011  *    notice, this list of conditions and the following disclaimer in the
0012  *    documentation and/or other materials provided with the distribution.
0013  *
0014  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0015  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0016  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0017  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0018  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0019  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0020  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0021  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0022  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0023  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0024  * SUCH DAMAGE.
0025  */
0026
0027 #include <sys/cdefs.h>
0028 #ifndef __rtems__
0029 __FBSDID("$FreeBSD$");
0030 #endif /* __rtems__ */
0031
0032 /*
0033  * The ELCR is a register that controls the trigger mode and polarity of
0034  * EISA and ISA interrupts.  In FreeBSD 3.x and 4.x, the ELCR was only
0035  * consulted for determining the appropriate trigger mode of EISA
0036  * interrupts when using an APIC.  However, it seems that almost all
0037  * systems that include PCI also include an ELCR that manages the ISA
0038  * IRQs 0 through 15.  Thus, we check for the presence of an ELCR on
0039  * every machine by checking to see if the values found at bootup are
0040  * sane.  Note that the polarity of ISA and EISA IRQs are linked to the
0041  * trigger mode.  All edge triggered IRQs use active-hi polarity, and
0042  * all level triggered interrupts use active-lo polarity.
0043  *
0044  * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
0045  * controls IRQ 0, bit 1 controls IRQ 1, etc.  If the bit is zero, the
0046  * associated IRQ is edge triggered.  If the bit is one, the IRQ is
0047  * level triggered.
0048  */
0049
0050 #ifndef __rtems__
0051 #include <sys/param.h>
0052 #include <sys/bus.h>
0053 #include <sys/systm.h>
0054 #include <machine/intr_machdep.h>
0055 #endif /* __rtems__ */
0056
0057 #ifdef __rtems__
0058 #include <bsp.h>
0059 #include "i386_io.h"
0060 #include <errno.h>
0061 #include "elcr.h"
0062 #endif /* __rtems__ */
0063
0064 #define ELCR_PORT   0x4d0
0065 #define ELCR_MASK(irq)  (1 << (irq))
0066
0067 static int elcr_status;
0068 #ifdef __rtems__
0069 static
0070 #endif /* __rtems__ */
0071 int elcr_found;
0072
0073 #ifdef __rtems__
0074 #undef printf
0075 #define printf printk
0076 #define bootverbose 1
0077 #define KASSERT(...)
0078 #endif /* __rtems__ */
0079
0080 /*
0081  * Check to see if we have what looks like a valid ELCR.  We do this by
0082  * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
0083  */
0084 int
0085 elcr_probe(void)
0086 {
0087     int i;
0088
0089     elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
0090     if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
0091         ELCR_MASK(8) | ELCR_MASK(13))) != 0)
0092         return (ENXIO);
0093     if (bootverbose) {
0094         printf("ELCR Found.  ISA IRQs programmed as:\n");
0095         for (i = 0; i < 16; i++)
0096             printf(" %2d", i);
0097         printf("\n");
0098         for (i = 0; i < 16; i++)
0099             if (elcr_status & ELCR_MASK(i))
0100                 printf("  L");
0101             else
0102                 printf("  E");
0103         printf("\n");
0104     }
0105 #ifndef __rtems__
0106     if (resource_disabled("elcr", 0))
0107         return (ENXIO);
0108 #endif /* __rtems__ */
0109     elcr_found = 1;
0110     return (0);
0111 }
0112
0113 /*
0114  * Returns 1 for level trigger, 0 for edge.
0115  */
0116 enum intr_trigger
0117 elcr_read_trigger(u_int irq)
0118 {
0119 #ifdef __rtems__
0120     if (!elcr_found)
0121         return INTR_TRIGGER_EDGE;
0122 #endif /* __rtems__ */
0123     KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
0124     KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
0125     if (elcr_status & ELCR_MASK(irq))
0126         return (INTR_TRIGGER_LEVEL);
0127     else
0128         return (INTR_TRIGGER_EDGE);
0129 }
0130
0131 /*
0132  * Set the trigger mode for a specified IRQ.  Mode of 0 means edge triggered,
0133  * and a mode of 1 means level triggered.
0134  */
0135 void
0136 elcr_write_trigger(u_int irq, enum intr_trigger trigger)
0137 {
0138     int new_status;
0139
0140 #ifdef __rtems__
0141     if (!elcr_found)
0142         return;
0143 #endif /* __rtems__ */
0144     KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
0145     KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
0146     if (trigger == INTR_TRIGGER_LEVEL)
0147         new_status = elcr_status | ELCR_MASK(irq);
0148     else
0149         new_status = elcr_status & ~ELCR_MASK(irq);
0150     if (new_status == elcr_status)
0151         return;
0152     elcr_status = new_status;
0153     if (irq >= 8)
0154         outb(ELCR_PORT + 1, elcr_status >> 8);
0155     else
0156         outb(ELCR_PORT, elcr_status & 0xff);
0157 }
0158
0159 void
0160 elcr_resume(void)
0161 {
0162 #ifdef __rtems__
0163     if (!elcr_found)
0164         return;
0165 #endif /* __rtems__ */
0166
0167     KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
0168     outb(ELCR_PORT, elcr_status & 0xff);
0169     outb(ELCR_PORT + 1, elcr_status >> 8);
0170 }