pc386/include/edid.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsI386
0005  *
0006  * @brief VESA EDID definitions.
0007  *
0008  * This file contains definitions for constants related to
0009  * VESA Extended Display Identification Data.
0010  *         More information can be found at
0011  *     <http://www.vesa.org/vesa-standards/free-standards/>
0012  *         VESA public standards may be found at
0013  *     <http://www.vesa.org/wp-content/uploads/2010/12/thankspublic.htm>
0014  */
0015
0016 /*
0017  * Copyright (C) 2014  Jan Doležal (dolezj21@fel.cvut.cz)
0018  *                     CTU in Prague.
0019  *
0020  *  The license and distribution terms for this file may be
0021  *  found in the file LICENSE in this distribution or at
0022  *  http://www.rtems.org/license/LICENSE.
0023  */
0024
0025 #ifndef _EDID_H
0026 #define _EDID_H
0027
0028 #ifndef ASM /* ASM */
0029
0030 #include <stdint.h>
0031
0032 #ifdef __cplusplus
0033 extern "C" {
0034 #endif /* __cplusplus */
0035
0036 #include <rtems/score/basedefs.h>
0037 #define EDID_INLINE_ROUTINE     static inline
0038
0039 /*  VESA Enhanced Extended Display Identification Data (E-EDID) Proposed
0040     Release A, March 27, 2007 */
0041
0042 /* *** Detailed Timing Descriptor Flags *** */
0043 #define EDID1_DTD_Flag_InterlacedOff            7
0044 #define EDID1_DTD_Flag_InterlacedMask           0x1
0045 #define EDID1_DTD_Flag_StereoModeOff            0
0046 #define EDID1_DTD_Flag_StereoModeMask           0xC1
0047 /* values for stereo flag */
0048 #define EDID1_DTD_Stereo_FldSeqRightOnSync      0x40
0049 #define EDID1_DTD_Stereo_FldSeqLeftOnSync       0x80
0050 #define EDID1_DTD_Stereo_2wItlvdRightOnEven     0x41
0051 #define EDID1_DTD_Stereo_2wItlvdLeftOnEven      0x81
0052 #define EDID1_DTD_Stereo_4wInterleaved          0xC0
0053 #define EDID1_DTD_Stereo_SideBySideItlvd        0xC1
0054 /* Analog = 0, Digital = 1 */
0055 #define EDID1_DTD_Flag_DigitalOff               4
0056 #define EDID1_DTD_Flag_DigitalMask              0x1
0057 /* Analog */
0058 #define EDID1_DTD_BipolarAnalogComposSyncOff    3
0059 #define EDID1_DTD_BipolarAnalogComposSyncMask   0x1
0060 #define EDID1_DTD_WithSerrationsOff             2
0061 #define EDID1_DTD_WithSerrationsMask            0x1
0062 /* Digital */
0063 #define EDID1_DTD_DigitalSeparateSyncOff        3
0064 #define EDID1_DTD_DigitalSeparateSyncMask       0x1
0065     /* when DigitalSeparateSync == 0 -> it is composite
0066        and WithSerrations defined up in Analog part applies */
0067 #define EDID1_DTD_VerticalSyncIsPositiveOff     2
0068 #define EDID1_DTD_VerticalSyncIsPositiveMask    0x1
0069 #define EDID1_DTD_HorizontalSyncIsPositiveOff   1
0070 #define EDID1_DTD_HorizontalSyncIsPositiveMask  0x1
0071
0072 typedef struct {
0073     uint8_t PixelClock_div10000[2];
0074     uint8_t HorizontalActiveLow;
0075     uint8_t HorizontalBlankingLow;
0076     uint8_t HorizontalBlanking_ActiveHigh;
0077     uint8_t VerticalActiveLow;
0078     uint8_t VerticalBlankingLow;
0079     uint8_t VerticalBlanking_ActiveHigh;
0080     uint8_t HorizontalSyncOffsetLow;
0081     uint8_t HorizontalSyncPulseWidthLow;
0082     uint8_t VerticalSyncPulseWidth_OffsetLow;
0083     uint8_t Vert_Hor_SyncPulseWidth_Offset_High;
0084     uint8_t HorizontalImageSizeLow;
0085     uint8_t VerticalImageSizeLow;
0086     uint8_t Vertical_HorizontalImageSizeHigh;
0087     uint8_t HorizontalBorder;
0088     uint8_t VerticalBorder;
0089     uint8_t Flags;
0090 } RTEMS_PACKED EDID_detailed_timing_descriptor;
0091
0092 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_active (
0093     EDID_detailed_timing_descriptor *dtd)
0094 {
0095     return (dtd->HorizontalActiveLow |
0096         (dtd->HorizontalBlanking_ActiveHigh & 0xF0) << 4);
0097 }
0098
0099 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_blanking (
0100     EDID_detailed_timing_descriptor *dtd)
0101 {
0102     return (dtd->HorizontalBlankingLow |
0103         (dtd->HorizontalBlanking_ActiveHigh & 0xF) << 8);
0104 }
0105
0106 EDID_INLINE_ROUTINE uint16_t DTD_vertical_active (
0107     EDID_detailed_timing_descriptor *dtd)
0108 {
0109     return (dtd->VerticalActiveLow |
0110         (dtd->VerticalBlanking_ActiveHigh & 0xF0) << 4);
0111 }
0112
0113 EDID_INLINE_ROUTINE uint16_t DTD_vertical_blanking (
0114     EDID_detailed_timing_descriptor *dtd)
0115 {
0116     return (dtd->VerticalBlankingLow |
0117         (dtd->VerticalBlanking_ActiveHigh & 0xF) << 8);
0118 }
0119
0120 EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_pulse_width (
0121     EDID_detailed_timing_descriptor *dtd)
0122 {
0123     return ((dtd->VerticalSyncPulseWidth_OffsetLow & 0xF) |
0124         (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x3) << 4);
0125 }
0126
0127 EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_offset (
0128     EDID_detailed_timing_descriptor *dtd)
0129 {
0130     return ((dtd->VerticalSyncPulseWidth_OffsetLow >> 4) |
0131         (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC) << 2);
0132 }
0133
0134 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_pulse_width (
0135     EDID_detailed_timing_descriptor *dtd)
0136 {
0137     return (dtd->HorizontalSyncPulseWidthLow |
0138         (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x30) << 4);
0139 }
0140
0141 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_offset (
0142     EDID_detailed_timing_descriptor *dtd)
0143 {
0144     return (dtd->HorizontalSyncOffsetLow |
0145         (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC0) << 2);
0146 }
0147
0148 EDID_INLINE_ROUTINE uint16_t DTD_vertical_image_size (
0149     EDID_detailed_timing_descriptor *dtd)
0150 {
0151     return (dtd->VerticalImageSizeLow |
0152         (dtd->Vertical_HorizontalImageSizeHigh & 0xF) << 8);
0153 }
0154
0155 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_image_size (
0156     EDID_detailed_timing_descriptor *dtd)
0157 {
0158     return (dtd->HorizontalImageSizeLow |
0159         (dtd->Vertical_HorizontalImageSizeHigh & 0xF0) << 4);
0160 }
0161
0162 typedef struct {
0163     uint8_t ColorPointWhitePointIndexNumber;
0164     uint8_t ColorPointWhiteLowBits;
0165     uint8_t ColorPointWhite_x;
0166     uint8_t ColorPointWhite_y;
0167     uint8_t ColorPointWhiteGamma;
0168 } RTEMS_PACKED EDID_color_point_data;
0169
0170 /* Basic Display Parameters */
0171 /* Monitor Descriptor - Data Type Tag */
0172 #define EDID_DTT_MonitorSerialNumber        0xFF
0173
0174 #define EDID_DTT_ASCIIString                0xFE
0175
0176 #define EDID_DTT_MonitorRangeLimits         0xFD
0177 typedef struct {
0178     uint8_t MinVerticalRateInHz;
0179     uint8_t MaxVerticalRateInHz;
0180     uint8_t MinHorizontalInKHz;
0181     uint8_t MaxHorizontalInKHz;
0182     uint8_t MaxSupportedPixelClockIn10MHz;
0183 /* see  VESA, Generalized Timing Formula Standard - GTF
0184         Version 1.0, December 18, 1996 */
0185     uint8_t GTFStandard[8];
0186 } RTEMS_PACKED EDID_monitor_range_limits;
0187
0188 #define EDID_DTT_MonitorName                0xFC
0189
0190 #define EDID_DTT_AdditionalColorPointData   0xFB
0191 /* Standard Timing Identification */
0192 #define EDID_DTT_AdditionalSTI              0xFA
0193
0194 #define EDID_DTT_DisplayColorManagement     0xF9
0195
0196 #define EDID_DTT_CVT3ByteTimingCodes        0xF8
0197
0198 #define EDID1_CVT_AspectRatioOff            2
0199 #define EDID1_CVT_AspectRatioMask           0x3
0200 #define EDID1_CVT_AddressableLinesHighOff   4
0201 #define EDID1_CVT_AddressableLinesHighMask  0xF
0202     /* next 5 bits indicate supported vertical rates */
0203 #define EDID1_CVT_VerticalRate60HzRBOff     0
0204 #define EDID1_CVT_VerticalRate60HzRBMask    0x1
0205 #define EDID1_CVT_VerticalRate85HzOff       1
0206 #define EDID1_CVT_VerticalRate85HzMask      0x1
0207 #define EDID1_CVT_VerticalRate75HzOff       2
0208 #define EDID1_CVT_VerticalRate75HzMask      0x1
0209 #define EDID1_CVT_VerticalRate60HzOff       3
0210 #define EDID1_CVT_VerticalRate60HzMask      0x1
0211 #define EDID1_CVT_VerticalRate50HzOff       4
0212 #define EDID1_CVT_VerticalRate50HzMask      0x1
0213 #define EDID1_CVT_PreferredVerticalRateOff  5
0214 #define EDID1_CVT_PreferredVerticalRateMask 0x3
0215
0216 #define EDID_CVT_AspectRatio_4_3            0
0217 #define EDID_CVT_AspectRatio_16_9           1
0218 #define EDID_CVT_AspectRatio_16_10          2
0219 #define EDID_CVT_AspectRatio_15_9           3
0220 #define EDID_CVT_PrefVertRate50Hz           0
0221 #define EDID_CVT_PrefVertRate60Hz           1
0222 #define EDID_CVT_PrefVertRate75Hz           2
0223 #define EDID_CVT_PrefVertRate85Hz           3
0224 typedef struct {
0225     uint8_t AddressableLinesLow;
0226     uint8_t AspectRatio_AddressableLinesHigh;
0227     uint8_t VerticalRate_PreferredVerticalRate;
0228 } RTEMS_PACKED EDID_CVT_3_byte_code_descriptor;
0229 typedef struct {
0230     uint8_t VersionNumber;
0231     EDID_CVT_3_byte_code_descriptor cvt[4];
0232 } RTEMS_PACKED EDID_CVT_timing_codes_3B;
0233
0234 EDID_INLINE_ROUTINE uint16_t edid1_CVT_addressable_lines_high (
0235     EDID_CVT_3_byte_code_descriptor *cvt)
0236 {
0237     return (cvt->AddressableLinesLow |
0238         (cvt->VerticalRate_PreferredVerticalRate &
0239          (EDID1_CVT_AddressableLinesHighMask<<EDID1_CVT_AddressableLinesHighOff)
0240         ) << (8-EDID1_CVT_AddressableLinesHighOff) );
0241 }
0242
0243 EDID_INLINE_ROUTINE uint8_t edid1_CVT_aspect_ratio (
0244     EDID_CVT_3_byte_code_descriptor *cvt)
0245 {
0246     return (cvt->AspectRatio_AddressableLinesHigh >> EDID1_CVT_AspectRatioOff) &
0247         EDID1_CVT_AspectRatioMask;
0248 }
0249
0250 #define EDID_DTT_EstablishedTimingsIII      0xF7
0251 typedef struct {
0252     uint8_t RevisionNumber;
0253     uint8_t EST_III[12];
0254 } RTEMS_PACKED EDID_established_timings_III;
0255 enum EST_III {
0256     EST_1152x864_75Hz   = 0,
0257     EST_1024x768_85Hz   = 1,
0258     EST_800x600_85Hz    = 2,
0259     EST_848x480_60Hz    = 3,
0260     EST_640x480_85Hz    = 4,
0261     EST_720x400_85Hz    = 5,
0262     EST_640x400_85Hz    = 6,
0263     EST_640x350_85Hz    = 7,
0264
0265     EST_1280x1024_85Hz  = 8,
0266     EST_1280x1024_60Hz  = 9,
0267     EST_1280x960_85Hz   = 10,
0268     EST_1280x960_60Hz   = 11,
0269     EST_1280x768_85Hz   = 12,
0270     EST_1280x768_75Hz   = 13,
0271     EST_1280x768_60Hz   = 14,
0272     EST_1280x768_60HzRB = 15,
0273
0274     EST_1400x1050_75Hz  = 16,
0275     EST_1400x1050_60Hz  = 17,
0276     EST_1400x1050_60HzRB= 18,
0277     EST_1400x900_85Hz   = 19,
0278     EST_1400x900_75Hz   = 20,
0279     EST_1400x900_60Hz   = 21,
0280     EST_1400x900_60HzRB = 22,
0281     EST_1360x768_60Hz   = 23,
0282
0283     EST_1600x1200_70Hz  = 24,
0284     EST_1600x1200_65Hz  = 25,
0285     EST_1600x1200_60Hz  = 26,
0286     EST_1680x1050_85Hz  = 27,
0287     EST_1680x1050_75Hz  = 28,
0288     EST_1680x1050_60Hz  = 29,
0289     EST_1680x1050_60HzRB= 30,
0290     EST_1400x1050_85Hz  = 31,
0291
0292     EST_1920x1200_60Hz  = 32,
0293     EST_1920x1200_60HzRB= 33,
0294     EST_1856x1392_75Hz  = 34,
0295     EST_1856x1392_60Hz  = 35,
0296     EST_1792x1344_75Hz  = 36,
0297     EST_1792x1344_60Hz  = 37,
0298     EST_1600x1200_85Hz  = 38,
0299     EST_1600x1200_75Hz  = 39,
0300
0301     EST_1920x1440_75Hz  = 44,
0302     EST_1920x1440_60Hz  = 45,
0303     EST_1920x1200_85Hz  = 46,
0304     EST_1920x1200_75Hz  = 47,
0305 };
0306
0307 #define EDID_DTT_DescriptorSpaceUnused      0x10
0308 /* DTT 0x0 - 0xF are manufacturer specific */
0309
0310 typedef struct {
0311     uint8_t Flag0[2];
0312     uint8_t Flag1;
0313     uint8_t DataTypeTag;
0314     uint8_t Flag2;
0315     uint8_t DescriptorData[13];
0316 } RTEMS_PACKED EDID_monitor_descriptor;
0317
0318 union EDID_DTD_MD {
0319     EDID_detailed_timing_descriptor dtd;
0320     EDID_monitor_descriptor md;
0321 } RTEMS_PACKED;
0322
0323 #define EDID1_STI_ImageAspectRatioOff           0
0324 #define EDID1_STI_ImageAspectRatioMask          0x3
0325 #define EDID1_STI_RefreshRateOff                2
0326 #define EDID1_STI_RefreshRateMask               0x3F
0327
0328 #define EDID_STI_DescriptorUnused           0x0101
0329 #define EDID_STI_AspectRatio_16_10          0
0330 #define EDID_STI_AspectRatio_4_3            1
0331 #define EDID_STI_AspectRatio_5_4            2
0332 #define EDID_STI_AspectRatio_16_9           3
0333 typedef struct {
0334     uint8_t HorizontalActivePixels;
0335     uint8_t ImageAspectRatio_RefreshRate;
0336 } RTEMS_PACKED EDID_standard_timing_identification;
0337
0338 /* Video Input Definition */
0339 /* Analog = 0, Digital = 1 */
0340 #define EDID1_VID_DigitalSignalLevelOff         7
0341 #define EDID1_VID_DigitalSignalLevelMask        0x1
0342 /* for EDID1_VID_DigitalSignalLevelOff = 1 (Digital) */
0343 #define EDID1_VID_ColorBitDepthOff              4
0344 #define EDID1_VID_ColorBitDepthMask             0x7 /* see CBD */
0345 #define EDID1_VID_DigitalVideoStandardSuppOff   0
0346 #define EDID1_VID_DigitalVideoStandardSuppMask  0xF /* see DVS */
0347 /* for EDID1_VID_DigitalSignalLevelOff = 0 (Analog) */
0348 #define EDID1_VID_SignalLevelStandardOff        5
0349 #define EDID1_VID_SignalLevelStandardMask       0x3
0350 #define EDID1_VID_VideoSetupBlankOff            4
0351 #define EDID1_VID_VideoSetupBlankMask           0x1
0352 #define EDID1_VID_SeparateSyncHandVSignalsOff   3
0353 #define EDID1_VID_SeparateSyncHandVSignalsMask  0x1
0354 #define EDID1_VID_SyncSignalOnHorizontalOff     2
0355 #define EDID1_VID_SyncSignalOnHorizontalMask    0x1
0356 #define EDID1_VID_SyncSignalOnGreenOff          1
0357 #define EDID1_VID_SyncSignalOnGreenMask         0x1
0358 #define EDID1_VID_SerationOnVerticalSyncOff     0
0359 #define EDID1_VID_SerationOnVerticalSyncMask    0x1
0360 /* Analog Interface Data Format - Signal Level Standard */
0361 #define EDID_SLS_0700_0300_1000Vpp             0x0
0362 #define EDID_SLS_0714_0286_1000Vpp             0x1
0363 #define EDID_SLS_1000_0400_1400Vpp             0x2
0364 #define EDID_SLS_0700_0000_0700Vpp             0x3
0365
0366 /* Color Bit Depths */
0367 #define CBD_undef               0x0
0368 #define CBD_6bPerPrimaryColor   0x1
0369 #define CBD_8bPerPrimaryColor   0x2
0370 #define CBD_10bPerPrimaryColor  0x3
0371 #define CBD_12bPerPrimaryColor  0x4
0372 #define CBD_14bPerPrimaryColor  0x5
0373 #define CBD_16bPerPrimaryColor  0x6
0374 #define CBD_reserved            0x7
0375
0376 /* Digital Video Standard Supported */
0377 #define DVS_undef               0x0
0378 #define DVS_DVI                 0x1
0379 #define DVS_HDMI_a              0x2
0380 #define DVS_HDMI_b              0x3
0381 #define DVS_MDDI                0x4
0382 #define DVS_DiplayPort          0x5
0383
0384 /* Feature Support */
0385 #define EDID1_Feature_GTFSupported_mask              0x1
0386 #define EDID1_Feature_GTFSupported_off               0
0387 #define EDID1_Feature_PreferredTimingMode_mask       0x1
0388 #define EDID1_Feature_PreferredTimingMode_off        1
0389 #define EDID1_Feature_StandardDefaultColorSpace_mask 0x1
0390 #define EDID1_Feature_StandardDefaultColorSpace_off  2
0391 #define EDID1_Feature_DisplayType_mask               0x2
0392 #define EDID1_Feature_DisplayType_off                3
0393         /* Refer to VESA DPMS Specification */
0394 #define EDID1_Feature_ActiveOff_mask                 0x1
0395 #define EDID1_Feature_ActiveOff_off                  5
0396 #define EDID1_Feature_Suspend_mask                   0x1
0397 #define EDID1_Feature_Suspend_off                    6
0398 #define EDID1_Feature_StandBy_mask                   0x1
0399 #define EDID1_Feature_StandBy_off                    7
0400     /* analog - Display Color Type */
0401 #define EDID_DisplayType_Monochrome                 0
0402 #define EDID_DisplayType_RGBcolor                   1
0403 #define EDID_DisplayType_nonRGBcolor                2
0404 #define EDID_DisplayType_undef                      3
0405     /* digital - Supported Color Encoding Formats */
0406 #define EDID_DisplayType_RGB444                     0
0407 #define EDID_DisplayType_RGB444YCrCb444             1
0408 #define EDID_DisplayType_RGB444YCrCb422             2
0409 #define EDID_DisplayType_RGB444YCrCb444YCrCb422     3
0410
0411 typedef struct {
0412     uint8_t Header[8];
0413 /*  Vendor Product Identification */
0414     uint8_t IDManufacturerName[2];
0415     uint8_t IDProductCode[2];
0416     uint8_t IDSerialNumber[4];
0417     uint8_t WeekofManufacture;
0418     uint8_t YearofManufacture;
0419 /*  EDID Structure Version Revision Level */
0420     uint8_t Version;
0421     uint8_t Revision;
0422 /*  Basic Display Parameters Features */
0423     /* Video Input Definition */
0424     uint8_t VideoInputDefinition;
0425     uint8_t MaxHorizontalImageSize;
0426     uint8_t MaxVerticalImageSize;
0427     uint8_t DisplayTransferCharacteristic;
0428     /* Feature Support */
0429     uint8_t Features;
0430 /*  Color Characteristics */
0431     uint8_t GreenRedLow;
0432     uint8_t WhiteBlueLow;
0433     uint8_t RedXHigh;
0434     uint8_t RedYHigh;
0435     uint8_t GreenXHigh;
0436     uint8_t GreenYHigh;
0437     uint8_t BlueXHigh;
0438     uint8_t BlueYHigh;
0439     uint8_t WhiteXHigh;
0440     uint8_t WhiteYHigh;
0441 /*  Established Timings I, II, Manufacturer's */
0442     uint8_t EST_I_II_Man[3];
0443 /*  Standard Timing Identification */
0444     EDID_standard_timing_identification STI[8];
0445 /*  Detailed Timing Descriptions / Monitor Descriptions */
0446     union EDID_DTD_MD dtd_md[4];
0447     uint8_t ExtensionFlag;
0448     uint8_t Checksum;
0449 } RTEMS_PACKED EDID_edid1;
0450
0451 EDID_INLINE_ROUTINE uint16_t edid1_RedX (EDID_edid1 *edid) {
0452     return (edid->RedXHigh<<2) | (edid->GreenRedLow>>6);
0453 }
0454 EDID_INLINE_ROUTINE uint16_t edid1_RedY (EDID_edid1 *edid) {
0455     return (edid->RedYHigh<<2) | (edid->GreenRedLow>>4)&&0x3;
0456 }
0457 EDID_INLINE_ROUTINE uint16_t edid1_GreenX (EDID_edid1 *edid) {
0458     return (edid->GreenXHigh<<2) | (edid->GreenRedLow>>2)&&0x3;
0459 }
0460 EDID_INLINE_ROUTINE uint16_t edid1_GreenY (EDID_edid1 *edid) {
0461     return (edid->GreenYHigh<<2) | (edid->GreenRedLow&0x3);
0462 }
0463 EDID_INLINE_ROUTINE uint16_t edid1_BlueX (EDID_edid1 *edid) {
0464     return (edid->BlueXHigh<<2)  | (edid->WhiteBlueLow>>6);
0465 }
0466 EDID_INLINE_ROUTINE uint16_t edid1_BlueY (EDID_edid1 *edid) {
0467     return (edid->BlueYHigh<<2)  | (edid->WhiteBlueLow>>4)&&0x3;
0468 }
0469 EDID_INLINE_ROUTINE uint16_t edid1_WhiteX (EDID_edid1 *edid) {
0470     return (edid->WhiteXHigh<<2) | (edid->WhiteBlueLow>>2)&&0x3;
0471 }
0472 EDID_INLINE_ROUTINE uint16_t edid1_WhiteY (EDID_edid1 *edid) {
0473     return (edid->WhiteYHigh<<2) | (edid->WhiteBlueLow&0x3);
0474 }
0475
0476 EDID_INLINE_ROUTINE int edid1_STI_is_unused (
0477       const EDID_standard_timing_identification *edid_sti) {
0478     return (edid_sti->HorizontalActivePixels ==
0479                   (uint8_t)EDID_STI_DescriptorUnused) &&
0480            (edid_sti->ImageAspectRatio_RefreshRate ==
0481                   (uint8_t)(EDID_STI_DescriptorUnused >> 8));
0482 }
0483
0484 enum edid1_established_timings {
0485 /*  Established Timings I */
0486     EST_800x600_60Hz    = 0,
0487     EST_800x600_56Hz    = 1,
0488     EST_640x480_75Hz    = 2,
0489     EST_640x480_72Hz    = 3,
0490     EST_640x480_67Hz    = 4,
0491     EST_640x480_60Hz    = 5,
0492     EST_720x400_88Hz    = 6,
0493     EST_720x400_70Hz    = 7,
0494 /*  Established Timings II */
0495     EST_1280x1024_75Hz  = 8,
0496     EST_1024x768_75Hz   = 9,
0497     EST_1024x768_70Hz   = 10,
0498     EST_1024x768_60Hz   = 11,
0499     EST_1024x768_87Hz   = 12,
0500     EST_832x624_75Hz    = 13,
0501     EST_800x600_75Hz    = 14,
0502     EST_800x600_72Hz    = 15,
0503 /*  Manufacturer's Timings */
0504     EST_1152x870_75Hz   = 23,
0505 };
0506
0507 EDID_INLINE_ROUTINE uint8_t edid1_established_tim (
0508     EDID_edid1 *edid,
0509     enum edid1_established_timings est)
0510 {
0511     return (uint8_t)(edid->EST_I_II_Man[est/8] & (est%8));
0512 }
0513
0514 #ifdef __cplusplus
0515 }
0516 #endif /* __cplusplus */
0517
0518 #endif /* ASM */
0519
0520 #endif /* _VBE_H */