i386/include/uart.h

0001 /**
0002  * @file
0003  * @ingroup i386_uart
0004  * @brief i386 UART definitions
0005  */
0006
0007 /*
0008  * This software is Copyright (C) 1998 by T.sqware - all rights limited
0009  * It is provided in to the public domain "as is", can be freely modified
0010  * as far as this copyight notice is kept unchanged, but does not imply
0011  * an endorsement by T.sqware of the product in which it is included.
0012  */
0013
0014 /**
0015  * @defgroup i386_uart UART
0016  * @ingroup i386_comm
0017  * @brief i386 UART definitions
0018  * @{
0019  */
0020
0021 #ifndef _BSPUART_H
0022 #define _BSPUART_H
0023
0024 #ifdef __cplusplus
0025 extern "C" {
0026 #endif
0027
0028 void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
0029 void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
0030 void BSP_uart_set_baud(int uart, unsigned long baud);
0031 void BSP_uart_intr_ctrl(int uart, int cmd);
0032 void BSP_uart_throttle(int uart);
0033 void BSP_uart_unthrottle(int uart);
0034 int  BSP_uart_polled_status(int uart);
0035 void BSP_uart_polled_write(int uart, int val);
0036 int  BSP_uart_polled_read(int uart);
0037 void BSP_uart_termios_set(int uart, void *ttyp);
0038 int  BSP_uart_termios_read_com1(int uart);
0039 int  BSP_uart_termios_read_com2(int uart);
0040 ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len);
0041 ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len);
0042 void BSP_uart_termios_isr_com1(void *);
0043 void BSP_uart_termios_isr_com2(void *);
0044 void BSP_uart_dbgisr_com1(void);
0045 void BSP_uart_dbgisr_com2(void);
0046 extern int BSP_poll_char_via_serial(void);
0047 extern void BSP_output_char_via_serial(char val);
0048 extern int BSPConsolePort;
0049 extern int BSPBaseBaud;
0050
0051 /** @brief
0052  * Command values for BSP_uart_intr_ctrl(),
0053  * values are strange in order to catch errors
0054  * with assert
0055  */
0056 #define BSP_UART_INTR_CTRL_DISABLE  (0)
0057 #define BSP_UART_INTR_CTRL_GDB      (0xaa) ///< RX only
0058 #define BSP_UART_INTR_CTRL_ENABLE   (0xbb) ///< Normal operations
0059 #define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) ///< RX & line status
0060
0061 /** @brief Return values for uart_polled_status() */
0062 #define BSP_UART_STATUS_ERROR    (-1) ///< No character
0063 #define BSP_UART_STATUS_NOCHAR   (0)  ///< No character
0064 #define BSP_UART_STATUS_CHAR     (1)  ///< Character present
0065 #define BSP_UART_STATUS_BREAK    (2)  ///< Break point is detected
0066
0067 /** @brief PC UART definitions */
0068 #define BSP_UART_COM1            (0)
0069 #define BSP_UART_COM2            (1)
0070
0071 /** @brief
0072  * Base IO for UART
0073  */
0074
0075 #define COM1_BASE_IO    0x3F8
0076 #define COM2_BASE_IO    0x2F8
0077
0078 /** @brief
0079  * Offsets from base
0080  */
0081
0082 /** @brief DLAB 0 */
0083 #define RBR  (0)    ///< Rx Buffer Register (read)
0084 #define THR  (0)    ///< Tx Buffer Register (write)
0085 #define IER  (1)    ///< Interrupt Enable Register
0086
0087 /** @brief DLAB X */
0088 #define IIR  (2)    ///< Interrupt Ident Register (read)
0089 #define FCR  (2)    ///< FIFO Control Register (write)
0090 #define LCR  (3)    ///< Line Control Register
0091 #define MCR  (4)    ///< Modem Control Register
0092 #define LSR  (5)    ///< Line Status Register
0093 #define MSR  (6)    ///< Modem Status  Register
0094 #define SCR  (7)    ///< Scratch register
0095
0096 /** @brief DLAB 1 */
0097 #define DLL  (0)    ///< Divisor Latch, LSB
0098 #define DLM  (1)    ///< Divisor Latch, MSB
0099 #define AFR  (2)    ///< Alternate Function register
0100
0101 /** @brief
0102  * Interrupt source definition via IIR
0103  */
0104 #define MODEM_STATUS                0
0105 #define NO_MORE_INTR                1
0106 #define TRANSMITTER_HODING_REGISTER_EMPTY   2
0107 #define RECEIVER_DATA_AVAIL         4
0108 #define RECEIVER_ERROR              6
0109 #define CHARACTER_TIMEOUT_INDICATION        12
0110
0111 /** @brief
0112  * Bits definition of IER
0113  */
0114 #define RECEIVE_ENABLE      0x1
0115 #define TRANSMIT_ENABLE     0x2
0116 #define RECEIVER_LINE_ST_ENABLE 0x4
0117 #define MODEM_ENABLE        0x8
0118 #define INTERRUPT_DISABLE   0x0
0119
0120 /** @brief
0121  * Bits definition of the Line Status Register (LSR)
0122  */
0123 #define DR  0x01    ///< Data Ready
0124 #define OE  0x02    ///< Overrun Error
0125 #define PE  0x04    ///< Parity Error
0126 #define FE  0x08    ///< Framing Error
0127 #define BI  0x10    ///< Break Interrupt
0128 #define THRE    0x20    ///< Transmitter Holding Register Empty
0129 #define TEMT    0x40    ///< Transmitter Empty
0130 #define ERFIFO  0x80    ///< Error receive Fifo
0131
0132 /** @brief
0133  * Bits definition of the MODEM Control Register (MCR)
0134  */
0135 #define DTR 0x01    ///< Data Terminal Ready
0136 #define RTS     0x02    ///< Request To Send
0137 #define OUT_1   0x04    ///< Output 1, (reserved on COMPAQ I/O Board)
0138 #define OUT_2   0x08    ///< Output 2, Enable Asynchronous Port Interrupts
0139 #define LB  0x10    ///< Enable Internal Loop Back
0140
0141 /** @brief
0142  * Bits definition of the Line Control Register (LCR)
0143  */
0144 #define CHR_5_BITS 0
0145 #define CHR_6_BITS 1
0146 #define CHR_7_BITS 2
0147 #define CHR_8_BITS 3
0148
0149 #define WL  0x03    ///< Word length mask
0150 #define STB 0x04    ///< 1 Stop Bit, otherwise 2 Stop Bits
0151 #define PEN 0x08    ///< Parity Enabled
0152 #define EPS 0x10    ///< Even Parity Select, otherwise Odd
0153 #define SP  0x20    ///< Stick Parity
0154 #define BCB 0x40    ///< Break Control Bit
0155 #define DLAB    0x80    ///< Enable Divisor Latch Access
0156
0157 /** @brief
0158  * Bits definition of the MODEM Status Register (MSR)
0159  */
0160 #define DCTS    0x01    ///< Delta Clear To Send
0161 #define DDSR    0x02    ///< Delta Data Set Ready
0162 #define TERI    0x04    ///< Trailing Edge Ring Indicator
0163 #define DDCD    0x08    ///< Delta Carrier Detect Indicator
0164 #define CTS     0x10    ///< Clear To Send (when loop back is active)
0165 #define DSR 0x20    ///< Data Set Ready (when loop back is active)
0166 #define RI      0x40    ///< Ring Indicator (when loop back is active)
0167 #define DCD 0x80    ///< Data Carrier Detect (when loop back is active)
0168
0169 /** @brief
0170  * Bits definition of the FIFO Control Register : WD16C552 or NS16550
0171  */
0172
0173 #define FIFO_CTRL   0x01    ///< Set to 1 permit access to other bits
0174 #define FIFO_EN     0x01    ///< Enable the FIFO
0175 #define XMIT_RESET  0x02    ///< Transmit FIFO Reset
0176 #define RCV_RESET   0x04    ///< Receive FIFO Reset
0177 #define FCR3        0x08    ///< do not understand manual!
0178
0179 #define RECEIVE_FIFO_TRIGGER1   0x0  ///< trigger recieve interrupt after 1 byte
0180 #define RECEIVE_FIFO_TRIGGER4   0x40 ///< trigger recieve interrupt after 4 byte
0181 #define RECEIVE_FIFO_TRIGGER8   0x80 ///< trigger recieve interrupt after 8 byte
0182 #define RECEIVE_FIFO_TRIGGER12  0xc0 ///< trigger recieve interrupt after 12 byte
0183 #define TRIG_LEVEL          0xc0 ///< Mask for the trigger level
0184
0185 /** @} */
0186
0187 #ifdef __cplusplus
0188 }
0189 #endif
0190
0191 #endif /* _BSPUART_H */