LXR |
|
|
|
|||
File indexing completed on 2025-05-11 08:23:40
0001 /** 0002 * @file 0003 * @ingroup i386_smp 0004 * @brief Intel MultiProcessor Specification (MPS) 0005 * version 1.1 and 1.4 SMP hardware control 0006 */ 0007 0008 /* 0009 * Author: Erich Boleyn <erich@uruk.org> 0010 * http://www.uruk.org/~erich/ 0011 * 0012 * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. 0013 * 0014 * Redistribution and use in source and binary forms, with or without 0015 * modification, are permitted provided that the following conditions 0016 * are met: 0017 * 1. Redistributions of source code must retain the above copyright 0018 * notice, this list of conditions and the following disclaimer. 0019 * 2. Redistributions in binary form must reproduce the above copyright 0020 * notice, this list of conditions and the following disclaimer in the 0021 * documentation and/or other materials provided with the distribution. 0022 * 3. The name of the author may not be used to endorse or promote products 0023 * derived from this software without specific prior written permission. 0024 * 0025 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 0026 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 0027 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 0028 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 0029 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 0030 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 0031 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 0032 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 0033 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 0034 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0035 */ 0036 0037 /* 0038 * Header file implementing Intel MultiProcessor Specification (MPS) 0039 * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, 0040 * with hooks for running correctly on a standard PC without the hardware. 0041 * 0042 * This file was created from information in the Intel MPS version 1.4 0043 * document, order number 242016-004, which can be ordered from the 0044 * Intel literature center. 0045 */ 0046 0047 /* 0048 * This file is based upon code by Eric Boleyn as documented above. 0049 * RTEMS support was added and minimal other changes were made. 0050 * This should make it easier to compare this file with the original 0051 * version. 0052 * 0053 * COPYRIGHT (c) 2011. 0054 * On-Line Applications Research Corporation (OAR). 0055 * 0056 * The license and distribution terms for this file may be 0057 * found in the file LICENSE in this distribution or at 0058 * http://www.rtems.org/license/LICENSE. 0059 */ 0060 0061 /** 0062 * @defgroup i386_smp SMP 0063 * @ingroup RTEMSBSPsI386 0064 * @brief 0065 * Header file implementing Intel MultiProcessor Specification (MPS) 0066 * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, 0067 * with hooks for running correctly on a standard PC without the hardware. 0068 */ 0069 0070 #ifndef _SMP_IMPS_H 0071 #define _SMP_IMPS_H 0072 0073 /* make sure "apic.h" is included */ 0074 #ifndef _APIC_H 0075 #error Must include "apic.h" before "smp-imps.h" 0076 #endif /* !_APIC_H */ 0077 0078 /* 0079 * Defines used. 0080 */ 0081 0082 #define IMPS_READ(x) (*((volatile unsigned *) (x))) 0083 #define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y)) 0084 0085 #ifdef IMPS_DEBUG 0086 #define IMPS_DEBUG_PRINT(x) KERNEL_PRINT(x) 0087 #else /* !IMPS_DEBUG */ 0088 #define IMPS_DEBUG_PRINT(x) 0089 #endif /* !IMPS_DEBUG */ 0090 0091 #define IMPS_MAX_CPUS APIC_BCAST_ID 0092 0093 /** @brief 0094 * This is the value that must be in the "sig" member of the MP 0095 * Floating Pointer Structure. 0096 */ 0097 #define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24)) 0098 #define IMPS_FPS_IMCRP_BIT 0x80 0099 #define IMPS_FPS_DEFAULT_MAX 7 0100 0101 /** @brief 0102 * This is the value that must be in the "sig" member of the MP 0103 * Configuration Table Header. 0104 */ 0105 #define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24)) 0106 0107 /** @brief 0108 * These are the "type" values for Base MP Configuration Table entries. 0109 */ 0110 #define IMPS_FLAG_ENABLED 1 0111 #define IMPS_BCT_PROCESSOR 0 0112 #define IMPS_CPUFLAG_BOOT 2 0113 #define IMPS_BCT_BUS 1 0114 #define IMPS_BCT_IOAPIC 2 0115 #define IMPS_BCT_IO_INTERRUPT 3 0116 #define IMPS_BCT_LOCAL_INTERRUPT 4 0117 #define IMPS_INT_INT 0 0118 #define IMPS_INT_NMI 1 0119 #define IMPS_INT_SMI 2 0120 #define IMPS_INT_EXTINT 3 0121 0122 0123 /* 0124 * Typedefs and data item definitions done here. 0125 */ 0126 0127 typedef struct imps_fps imps_fps; ///< MP floating pointer structure 0128 typedef struct imps_cth imps_cth; ///< MP configuration table header 0129 typedef struct imps_processor imps_processor; 0130 typedef struct imps_bus imps_bus; 0131 typedef struct imps_ioapic imps_ioapic; 0132 typedef struct imps_interrupt imps_interrupt; 0133 0134 0135 /* 0136 * Data structures defined here 0137 */ 0138 0139 /** @brief 0140 * MP Floating Pointer Structure (fps) 0141 * 0142 * Look at page 4-3 of the MP spec for the starting definitions of 0143 * this structure. 0144 */ 0145 struct imps_fps 0146 { 0147 unsigned sig; 0148 imps_cth *cth_ptr; 0149 unsigned char length; 0150 unsigned char spec_rev; 0151 unsigned char checksum; 0152 unsigned char feature_info[5]; 0153 }; 0154 0155 /** @brief 0156 * MP Configuration Table Header (cth) 0157 * 0158 * Look at page 4-5 of the MP spec for the starting definitions of 0159 * this structure. 0160 */ 0161 struct imps_cth 0162 { 0163 unsigned sig; 0164 unsigned short base_length; 0165 unsigned char spec_rev; 0166 unsigned char checksum; 0167 char oem_id[8]; 0168 char prod_id[12]; 0169 unsigned oem_table_ptr; 0170 unsigned short oem_table_size; 0171 unsigned short entry_count; 0172 unsigned lapic_addr; 0173 unsigned short extended_length; 0174 unsigned char extended_checksum; 0175 char reserved[1]; 0176 }; 0177 0178 /** @brief 0179 * Base MP Configuration Table Types. They are sorted according to 0180 * type (i.e. all of type 0 come first, etc.). Look on page 4-6 for 0181 * the start of the descriptions. 0182 */ 0183 0184 struct imps_processor 0185 { 0186 unsigned char type; ///< must be 0 0187 unsigned char apic_id; 0188 unsigned char apic_ver; 0189 unsigned char flags; 0190 unsigned signature; 0191 unsigned features; 0192 char reserved[8]; 0193 }; 0194 0195 struct imps_bus 0196 { 0197 unsigned char type; ///< must be 1 0198 unsigned char id; 0199 char bus_type[6]; 0200 }; 0201 0202 struct imps_ioapic 0203 { 0204 unsigned char type; ///< must be 2 0205 unsigned char id; 0206 unsigned char ver; 0207 unsigned char flags; 0208 unsigned addr; 0209 }; 0210 0211 struct imps_interrupt 0212 { 0213 unsigned char type; ///< must be 3 or 4 0214 unsigned char int_type; 0215 unsigned short flags; 0216 unsigned char source_bus_id; 0217 unsigned char source_bus_irq; 0218 unsigned char dest_apic_id; 0219 unsigned char dest_apic_intin; 0220 }; 0221 0222 /* 0223 * Exported globals here. 0224 */ 0225 0226 /** @brief 0227 * These map from virtual cpu numbers to APIC id's and back. 0228 */ 0229 extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS]; 0230 extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS]; 0231 0232 /** @brief base address of application processor reset code at 0x70000 */ 0233 extern char _binary_appstart_bin_start[]; 0234 extern char _binary_appstart_bin_size[]; 0235 0236 /** @brief base address of the local apic. Usually 0xFEE00000 */ 0237 extern unsigned imps_lapic_addr; 0238 0239 /* 0240 * Defines that use variables 0241 */ 0242 #define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x)))) 0243 #define IMPS_LAPIC_WRITE(x, y) \ 0244 (*((volatile unsigned *) (imps_lapic_addr+(x))) = (y)) 0245 0246 #endif /* !_SMP_IMPS_H */ 0247 0248 /** @} */
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|