include/bsp/irq_asm.h

0001 /**
0002  * @file
0003  * @ingroup i386_irq
0004  * @brief
0005  */
0006
0007 /* irq_asm.h
0008  *
0009  *  This include file has defines to represent some contant used
0010  *  to program and manage the  Intel 8259 interrupt controller
0011  *
0012  *
0013  *  COPYRIGHT (c) 1998 valette@crf.canon.fr
0014  *
0015  *  Copyright (c) 2016 Chris Johns <chrisj@rtems.org>
0016  *
0017  *  The license and distribution terms for this file may be
0018  *  found in the file LICENSE in this distribution or at
0019  *  http://www.rtems.org/license/LICENSE.
0020  */
0021 #ifndef __I8259S_H__
0022 #define __I8259S_H__
0023
0024 #define BSP_ASM_IRQ_VECTOR_BASE 0x20
0025     /** @brief PIC's command and mask registers */
0026 #define PIC_MASTER_COMMAND_IO_PORT      0x20    ///< Master PIC command register
0027 #define PIC_SLAVE_COMMAND_IO_PORT       0xa0    ///< Slave PIC command register
0028 #define PIC_MASTER_IMR_IO_PORT          0x21    ///< Master PIC Interrupt Mask Register
0029 #define PIC_SLAVE_IMR_IO_PORT           0xa1    ///< Slave PIC Interrupt Mask Register
0030
0031     /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
0032 #define PIC_EOSI    0x60    ///< End of Specific Interrupt (EOSI)
0033 #define PIC_EOI     0x20    ///< Generic End of Interrupt (EOI)
0034
0035 /* Operation control word type 3.  Bit 3 (0x08) must be set. Even address. */
0036 #define PIC_OCW3_RIS        0x01            /* 1 = read IS, 0 = read IR */
0037 #define PIC_OCW3_RR         0x02            /* register read */
0038 #define PIC_OCW3_P          0x04            /* poll mode command */
0039 /* 0x08 must be 1 to select OCW3 vs OCW2 */
0040 #define PIC_OCW3_SEL        0x08            /* must be 1 */
0041 /* 0x10 must be 0 to select OCW3 vs ICW1 */
0042 #define PIC_OCW3_SMM        0x20            /* special mode mask */
0043 #define PIC_OCW3_ESMM       0x40            /* enable SMM */
0044
0045 #endif