include/libcpu/uartRegs.h

0001 /*  Blackfin UART Registers
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #ifndef _uartRegs_h_
0012 #define _uartRegs_h_
0013
0014 /* register addresses */
0015
0016 #define UART_RBR_OFFSET                               0x0000
0017 #define UART_THR_OFFSET                               0x0000
0018 #define UART_DLL_OFFSET                               0x0000
0019 #define UART_IER_OFFSET                               0x0004
0020 #define UART_DLH_OFFSET                               0x0004
0021 #define UART_IIR_OFFSET                               0x0008
0022 #define UART_LCR_OFFSET                               0x000c
0023 #define UART_MCR_OFFSET                               0x0010
0024 #define UART_LSR_OFFSET                               0x0014
0025 #define UART_SCR_OFFSET                               0x001c
0026 #define UART_GCTL_OFFSET                              0x0024
0027
0028
0029 /* register fields */
0030
0031 #define UART_LCR_DLAB                                   0x80
0032 #define UART_LCR_SB                                     0x40
0033 #define UART_LCR_STP                                    0x20
0034 #define UART_LCR_EPS                                    0x10
0035 #define UART_LCR_PEN                                    0x08
0036 #define UART_LCR_STB                                    0x04
0037 #define UART_LCR_WLS_MASK                               0x03
0038 #define UART_LCR_WLS_5                                  0x00
0039 #define UART_LCR_WLS_6                                  0x01
0040 #define UART_LCR_WLS_7                                  0x02
0041 #define UART_LCR_WLS_8                                  0x03
0042
0043 #define UART_MCR_LOOP                                   0x10
0044
0045 #define UART_LSR_TEMT                                   0x40
0046 #define UART_LSR_THRE                                   0x20
0047 #define UART_LSR_BI                                     0x10
0048 #define UART_LSR_FE                                     0x08
0049 #define UART_LSR_PE                                     0x04
0050 #define UART_LSR_OE                                     0x02
0051 #define UART_LSR_DR                                     0x01
0052
0053 #define UART_IER_ELSI                                   0x04
0054 #define UART_IER_ETBEI                                  0x02
0055 #define UART_IER_ERBFI                                  0x01
0056
0057 #define UART_IIR_STATUS_MASK                            0x06
0058 #define UART_IIR_STATUS_THRE                            0x02
0059 #define UART_IIR_STATUS_RDR                             0x04
0060 #define UART_IIR_STATUS_LS                              0x06
0061 #define UART_IIR_NINT                                   0x01
0062
0063 #define UART_GCTL_FFE                                   0x20
0064 #define UART_GCTL_FPE                                   0x10
0065 #define UART_GCTL_RPOLC                                 0x08
0066 #define UART_GCTL_TPOLC                                 0x04
0067 #define UART_GCTL_IREN                                  0x02
0068 #define UART_GCTL_UCEN                                  0x01
0069
0070 #endif /* _uartRegs_h_ */