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File indexing completed on 2025-05-11 08:23:40

0001 /*  Blackfin System Interrupt Controller Registers
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010 
0011 #ifndef _sicRegs_h_
0012 #define _sicRegs_h_
0013 
0014 /* register addresses */
0015 
0016 #define SIC_IMASK                (SIC_BASE_ADDRESS + 0x000c)
0017 #define SIC_IMASK_PITCH          (0x40)
0018 
0019 #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
0020 #define SIC_ISR_PITCH            (0x40)
0021 
0022 #define SIC_IAR_BASE_ADDRESS     (SIC_BASE_ADDRESS + 0x0010)
0023 #define SIC_IAR_PITCH                                   0x04
0024 
0025 #define SIC_IAR0                 (SIC_BASE_ADDRESS + 0x0010)
0026 #if SIC_IAR_COUNT > 1
0027 #define SIC_IAR1                 (SIC_BASE_ADDRESS + 0x0014)
0028 #endif
0029 #if SIC_IAR_COUNT > 2
0030 #define SIC_IAR2                 (SIC_BASE_ADDRESS + 0x0018)
0031 #endif
0032 #if SIC_IAR_COUNT > 3
0033 #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
0034 #endif
0035 
0036 #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
0037 
0038 
0039 /* register fields */
0040 
0041 
0042 
0043 #endif /* _sicRegs_h_ */