include/libcpu/ppiRegs.h

0001 /*  Blackfin Parallel Peripheral Interface Registers
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #ifndef _ppiRegs_h_
0012 #define _ppiRegs_h_
0013
0014
0015 /* register addresses */
0016
0017 #define PPI_CONTROL_OFFSET                            0x0000
0018 #define PPI_STATUS_OFFSET                             0x0004
0019 #define PPI_COUNT_OFFSET                              0x0008
0020 #define PPI_DELAY_OFFSET                              0x000c
0021 #define PPI_FRAME_OFFSET                              0x0010
0022
0023
0024 /* register fields */
0025
0026 #define PPI_CONTROL_POLS                              0x8000
0027 #define PPI_CONTROL_POLC                              0x4000
0028 #define PPI_CONTROL_DLEN_MASK                         0x3800
0029 #define PPI_CONTROL_DLEN_8                            0x0000
0030 #define PPI_CONTROL_DLEN_10                           0x0800
0031 #define PPI_CONTROL_DLEN_11                           0x1000
0032 #define PPI_CONTROL_DLEN_12                           0x1800
0033 #define PPI_CONTROL_DLEN_13                           0x2000
0034 #define PPI_CONTROL_DLEN_14                           0x2800
0035 #define PPI_CONTROL_DLEN_15                           0x3000
0036 #define PPI_CONTROL_DLEN_16                           0x3800
0037 #define PPI_CONTROL_SKIP_EO                           0x0400
0038 #define PPI_CONTROL_SKIP_EN                           0x0200
0039 #define PPI_CONTROL_PACK_EN                           0x0080
0040 #define PPI_CONTROL_FLD_SEL                           0x0040
0041 #define PPI_CONTROL_PORT_CFG_MASK                     0x0030
0042 #define PPI_CONTROL_PORT_CFG_SHIFT                         4
0043 #define PPI_CONTROL_XFR_TYPE_MASK                     0x000c
0044 #define PPI_CONTROL_XFR_TYPE_SHIFT                         2
0045 #define PPI_CONTROL_PORT_DIR                          0x0002
0046 #define PPI_CONTROL_PORT_EN                           0x0001
0047
0048 #define PPI_STATUS_ERR_NCOR                           0x8000
0049 #define PPI_STATUS_ERR_DET                            0x4000
0050 #define PPI_STATUS_UNDR                               0x2000
0051 #define PPI_STATUS_OVR                                0x1000
0052 #define PPI_STATUS_FT_ERR                             0x0800
0053 #define PPI_STATUS_FLD                                0x0400
0054 #define PPI_STATUS_LT_ERR_UNDR                        0x0200
0055 #define PPI_STATUS_LT_ERR_OVR                         0x0100
0056
0057
0058 #endif /* _ppiRegs_h_ */