include/libcpu/mmu.h

0001 /*  Blackfin MMU Support
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011
0012 /* NOTE: this currently only implements a static table.  It should be made
0013    to handle more regions than fit in the CPLBs, with an exception handler
0014    to do replacements as needed.  This would of course require great care
0015    to insure any storage required by the exception handler, including any
0016    stack space, the exception handler itself, and the region descriptors
0017    it needs to update the CPLBs, are in regions that will never be
0018    replaced. */
0019
0020 #ifndef _mmu_h_
0021 #define _mmu_h_
0022
0023 #include <libcpu/mmuRegs.h>
0024
0025
0026 #define INSTR_NOCACHE   (ICPLB_DATA_CPLB_USER_RD | \
0027                          ICPLB_DATA_CPLB_VALID)
0028
0029 #define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \
0030                          ICPLB_DATA_CPLB_USER_RD | \
0031                          ICPLB_DATA_CPLB_VALID)
0032
0033 #define DATA_NOCACHE   (DCPLB_DATA_CPLB_DIRTY | \
0034                         DCPLB_DATA_CPLB_SUPV_WR | \
0035                         DCPLB_DATA_CPLB_USER_WR | \
0036                         DCPLB_DATA_CPLB_USER_RD | \
0037                         DCPLB_DATA_CPLB_VALID)
0038
0039 #define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \
0040                         DCPLB_DATA_CPLB_L1_CHBL | \
0041                         DCPLB_DATA_CPLB_DIRTY | \
0042                         DCPLB_DATA_CPLB_SUPV_WR | \
0043                         DCPLB_DATA_CPLB_USER_WR | \
0044                         DCPLB_DATA_CPLB_USER_RD | \
0045                         DCPLB_DATA_CPLB_VALID)
0046
0047
0048 #ifdef __cplusplus
0049 extern "C" {
0050 #endif
0051
0052
0053 typedef struct {
0054   struct {
0055     void *address;
0056     uint32_t flags;
0057   } instruction[ICPLB_COUNT];
0058   struct {
0059     void *address;
0060     uint32_t flags;
0061   } data[DCPLB_COUNT];
0062 } bfin_mmu_config_t;
0063
0064
0065 void bfin_mmu_init(bfin_mmu_config_t *config);
0066
0067
0068 #ifdef __cplusplus
0069 }
0070 #endif
0071
0072 #endif /* _mmu_h_ */
0073