include/libcpu/memoryRegs.h

0001 /*  Blackfin Memory Registers
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #ifndef _memoryRegs_h_
0012 #define _memoryRegs_h_
0013
0014 /* register addresses */
0015 #define DMEM_CONTROL                              0xffe00004
0016 #define DTEST_COMMAND                             0xffe00300
0017 #define DTEST_DATA0                               0xffe00400
0018 #define DTEST_DATA1                               0xffe00404
0019
0020 #define IMEM_CONTROL                              0xffe01004
0021
0022
0023 /* register fields */
0024 #define DMEM_CONTROL_PORT_PREF1                   0x00002000
0025 #define DMEM_CONTROL_PORT_PREF0                   0x00001000
0026 #define DMEM_CONTROL_DCBS                         0x00000010
0027 #define DMEM_CONTROL_DMC_MASK                     0x0000000c
0028 #define DMEM_CONTROL_DMC_SHIFT                             2
0029 #define DMEM_CONTROL_ENDCPLB                      0x00000002
0030
0031 #define DTEST_COMMAND_ACCESS_WAY1                 0x02000000
0032 #define DTEST_COMMAND_ACCESS_INSTRUCTION          0x01000000
0033 #define DTEST_COMMAND_ACCESS_BANKB                0x00800000
0034 #define DTEST_COMMAND_SRAM_ADDR_13_12_MASK        0x00030000
0035 #define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT               16
0036 #define DTEST_COMMAND_DATA_CACHE_SELECT           0x00004000
0037 #define DTEST_COMMAND_SET_INDEX_MASK              0x000007e0
0038 #define DTEST_COMMAND_SET_INDEX_SHIFT                      5
0039 #define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK      0x00000018
0040 #define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT              3
0041 #define DTEST_COMMAND_ACCESS_DATA_ARRAY           0x00000004
0042 #define DTEST_COMMAND_WRITE_ACCESS                0x00000002
0043
0044 #define DTEST_DATA0_TAG_19_2_MASK                 0xffffc000
0045 #define DTEST_DATA0_TAG_19_2_SHIFT                        14
0046 #define DTEST_DATA0_TAG                           0x00000800
0047 #define DTEST_DATA0_LRU                           0x00000004
0048 #define DTEST_DATA0_DIRTY                         0x00000002
0049 #define DTEST_DATA0_VALID                         0x00000001
0050
0051 #define IMEM_CONTROL_LRUPRIORST                   0x00002000
0052 #define IMEM_CONTROL_ILOC_MASK                    0x00000078
0053 #define IMEM_CONTROL_ILOC_SHIFT                            3
0054 #define IMEM_CONTROL_IMC                          0x00000004
0055 #define IMEM_CONTROL_ENICPLB                      0x00000002
0056
0057
0058 #endif /* _memoryRegs_h_ */