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File indexing completed on 2025-05-11 08:23:40

0001 /*  Blackfin Ethernet Registers
0002  *
0003  *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
0004  *             written by Allan Hessenflow <allanh@kallisti.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010 
0011 #ifndef _ethernetRegs_h_
0012 #define _ethernetRegs_h_
0013 
0014 /* register addresses */
0015 
0016 #define EMAC_OPMODE_OFFSET                            0x0000
0017 #define EMAC_ADDRLO_OFFSET                            0x0004
0018 #define EMAC_ADDRHI_OFFSET                            0x0008
0019 #define EMAC_HASHLO_OFFSET                            0x000c
0020 #define EMAC_HASHHI_OFFSET                            0x0010
0021 #define EMAC_STAADD_OFFSET                            0x0014
0022 #define EMAC_STADAT_OFFSET                            0x0018
0023 #define EMAC_FLC_OFFSET                               0x001c
0024 #define EMAC_VLAN1_OFFSET                             0x0020
0025 #define EMAC_VLAN2_OFFSET                             0x0024
0026 #define EMAC_WKUP_CTL_OFFSET                          0x002c
0027 #define EMAC_WKUP_FFMSK0_OFFSET                       0x0030
0028 #define EMAC_WKUP_FFMSK1_OFFSET                       0x0034
0029 #define EMAC_WKUP_FFMSK2_OFFSET                       0x0038
0030 #define EMAC_WKUP_FFMSK3_OFFSET                       0x003c
0031 #define EMAC_WKUP_FFCMD_OFFSET                        0x0040
0032 #define EMAC_WKUP_FFOFF_OFFSET                        0x0044
0033 #define EMAC_WKUP_FFCRC01_OFFSET                      0x0048
0034 #define EMAC_WKUP_FFCRC23_OFFSET                      0x004c
0035 #define EMAC_SYSCTL_OFFSET                            0x0060
0036 #define EMAC_SYSTAT_OFFSET                            0x0064
0037 #define EMAC_RX_STAT_OFFSET                           0x0068
0038 #define EMAC_RX_STKY_OFFSET                           0x006c
0039 #define EMAC_RX_IRQE_OFFSET                           0x0070
0040 #define EMAC_TX_STAT_OFFSET                           0x0074
0041 #define EMAC_TX_STKY_OFFSET                           0x0078
0042 #define EMAC_TX_IRQE_OFFSET                           0x007c
0043 #define EMAC_MMC_CTL_OFFSET                           0x0080
0044 #define EMAC_MMC_RIRQS_OFFSET                         0x0084
0045 #define EMAC_MMC_RIRQE_OFFSET                         0x0088
0046 #define EMAC_MMC_TIRQS_OFFSET                         0x008c
0047 #define EMAC_MMC_TIRQE_OFFSET                         0x0090
0048 
0049 #define EMAC_RXC_OK_OFFSET                            0x0100
0050 #define EMAC_RXC_FCS_OFFSET                           0x0104
0051 #define EMAC_RXC_ALIGN_OFFSET                         0x0108
0052 #define EMAC_RXC_OCTET_OFFSET                         0x010c
0053 #define EMAC_RXC_DMAOVF_OFFSET                        0x0110
0054 #define EMAC_RXC_UNICST_OFFSET                        0x0114
0055 #define EMAC_RXC_MULTI_OFFSET                         0x0118
0056 #define EMAC_RXC_BROAD_OFFSET                         0x011c
0057 #define EMAC_RXC_LNERRI_OFFSET                        0x0120
0058 #define EMAC_RXC_LNERRO_OFFSET                        0x0124
0059 #define EMAC_RXC_LONG_OFFSET                          0x0128
0060 #define EMAC_RXC_MACCTL_OFFSET                        0x012c
0061 #define EMAC_RXC_OPCODE_OFFSET                        0x0130
0062 #define EMAC_RXC_PAUSE_OFFSET                         0x0134
0063 #define EMAC_RXC_ALLFRM_OFFSET                        0x0138
0064 #define EMAC_RXC_ALLOCT_OFFSET                        0x013c
0065 #define EMAC_RXC_TYPED_OFFSET                         0x0140
0066 #define EMAC_RXC_SHORT_OFFSET                         0x0144
0067 #define EMAC_RXC_EQ64_OFFSET                          0x0148
0068 #define EMAC_RXC_LT128_OFFSET                         0x014c
0069 #define EMAC_RXC_LT256_OFFSET                         0x0150
0070 #define EMAC_RXC_LT512_OFFSET                         0x0154
0071 #define EMAC_RXC_LT1024_OFFSET                        0x0158
0072 #define EMAC_RXC_GE1024_OFFSET                        0x015c
0073 
0074 #define EMAC_TXC_OK_OFFSET                            0x0180
0075 #define EMAC_TXC_1COL_OFFSET                          0x0184
0076 #define EMAC_TXC_GT1COL_OFFSET                        0x0188
0077 #define EMAC_TXC_OCTET_OFFSET                         0x018c
0078 #define EMAC_TXC_DEFER_OFFSET                         0x0190
0079 #define EMAC_TXC_LATECL_OFFSET                        0x0194
0080 #define EMAC_TXC_XS_COL_OFFSET                        0x0198
0081 #define EMAC_TXC_DMAUND_OFFSET                        0x019c
0082 #define EMAC_TXC_CRSERR_OFFSET                        0x01a0
0083 #define EMAC_TXC_UNICST_OFFSET                        0x01a4
0084 #define EMAC_TXC_MULTI_OFFSET                         0x01a8
0085 #define EMAC_TXC_BROAD_OFFSET                         0x01ac
0086 #define EMAC_TXC_ES_DFR_OFFSET                        0x01b0
0087 #define EMAC_TXC_MACCTL_OFFSET                        0x01b4
0088 #define EMAC_TXC_ALLFRM_OFFSET                        0x01b8
0089 #define EMAC_TXC_ALLOCT_OFFSET                        0x01bc
0090 #define EMAC_TXC_EQ64_OFFSET                          0x01c0
0091 #define EMAC_TXC_LT128_OFFSET                         0x01c4
0092 #define EMAC_TXC_LT256_OFFSET                         0x01c8
0093 #define EMAC_TXC_LT512_OFFSET                         0x01cc
0094 #define EMAC_TXC_LT1024_OFFSET                        0x01d0
0095 #define EMAC_TXC_GE1024_OFFSET                        0x01d4
0096 #define EMAC_TXC_ABORT_OFFSET                         0x01d8
0097 
0098 
0099 /* register fields */
0100 
0101 #define EMAC_OPMODE_DRO                           0x10000000
0102 #define EMAC_OPMODE_LB                            0x08000000
0103 #define EMAC_OPMODE_FDMODE                        0x04000000
0104 #define EMAC_OPMODE_RMII_10                       0x02000000
0105 #define EMAC_OPMODE_RMII                          0x01000000
0106 #define EMAC_OPMODE_LCTRE                         0x00800000
0107 #define EMAC_OPMODE_DRTY                          0x00400000
0108 #define EMAC_OPMODE_BOLMT_MASK                    0x00300000
0109 #define EMAC_OPMODE_BOLMT_1023                    0x00000000
0110 #define EMAC_OPMODE_BOLMT_255                     0x00100000
0111 #define EMAC_OPMODE_BOLMT_15                      0x00200000
0112 #define EMAC_OPMODE_BOLMT_1                       0x00300000
0113 #define EMAC_OPMODE_DC                            0x00080000
0114 #define EMAC_OPMODE_DTXCRC                        0x00040000
0115 #define EMAC_OPMODE_DTXPAD                        0x00020000
0116 #define EMAC_OPMODE_TE                            0x00010000
0117 #define EMAC_OPMODE_RAF                           0x00001000
0118 #define EMAC_OPMODE_PSF                           0x00000800
0119 #define EMAC_OPMODE_PBF                           0x00000400
0120 #define EMAC_OPMODE_DBF                           0x00000200
0121 #define EMAC_OPMODE_IFE                           0x00000100
0122 #define EMAC_OPMODE_PR                            0x00000080
0123 #define EMAC_OPMODE_PAM                           0x00000040
0124 #define EMAC_OPMODE_HM                            0x00000020
0125 #define EMAC_OPMODE_HU                            0x00000010
0126 #define EMAC_OPMODE_ASTP                          0x00000002
0127 #define EMAC_OPMODE_RE                            0x00000001
0128 
0129 #define EMAC_STAADD_PHYAD_MASK                    0x0000f800
0130 #define EMAC_STAADD_PHYAD_SHIFT                           11
0131 #define EMAC_STAADD_REGAD_MASK                    0x000007c0
0132 #define EMAC_STAADD_REGAD_SHIFT                            6
0133 #define EMAC_STAADD_STAIE                         0x00000008
0134 #define EMAC_STAADD_STADISPRE                     0x00000004
0135 #define EMAC_STAADD_STAOP                         0x00000002
0136 #define EMAC_STAADD_STABUSY                       0x00000001
0137 
0138 #define EMAC_FLC_FLCPAUSE_MASK                    0xffff0000
0139 #define EMAC_FLC_FLCPAUSE_SHIFT                           16
0140 #define EMAC_FLC_BKPRSEN                          0x00000008
0141 #define EMAC_FLC_PCF                              0x00000004
0142 #define EMAC_FLC_FLCE                             0x00000002
0143 #define EMAC_FLC_FLCBUSY                          0x00000001
0144 
0145 #define EMAC_WKUP_CTL_RWKS_MASK                   0x00000f00
0146 #define EMAC_WKUP_CTL_RWKS_SHIFT                           8
0147 #define EMAC_WKUP_CTL_MPKS                        0x00000020
0148 #define EMAC_WKUP_CTL_GUWKE                       0x00000008
0149 #define EMAC_WKUP_CTL_RWKE                        0x00000004
0150 #define EMAC_WKUP_CTL_MPKE                        0x00000002
0151 #define EMAC_WKUP_CTL_CAPWKFRM                    0x00000001
0152 
0153 #define EMAC_WKUP_FFCMD_3_TYPE                    0x08000000
0154 #define EMAC_WKUP_FFCMD_3_EN                      0x01000000
0155 #define EMAC_WKUP_FFCMD_2_TYPE                    0x00080000
0156 #define EMAC_WKUP_FFCMD_2_EN                      0x00010000
0157 #define EMAC_WKUP_FFCMD_1_TYPE                    0x00000800
0158 #define EMAC_WKUP_FFCMD_1_EN                      0x00000100
0159 #define EMAC_WKUP_FFCMD_0_TYPE                    0x00000008
0160 #define EMAC_WKUP_FFCMD_0_EN                      0x00000001
0161 
0162 #define EMAC_WKUP_FFOFF_3_MASK                    0xff000000
0163 #define EMAC_WKUP_FFOFF_3_SHIFT                           24
0164 #define EMAC_WKUP_FFOFF_2_MASK                    0x00ff0000
0165 #define EMAC_WKUP_FFOFF_2_SHIFT                           16
0166 #define EMAC_WKUP_FFOFF_1_MASK                    0x0000ff00
0167 #define EMAC_WKUP_FFOFF_1_SHIFT                            8
0168 #define EMAC_WKUP_FFOFF_0_MASK                    0x000000ff
0169 #define EMAC_WKUP_FFOFF_0_SHIFT                            0
0170 
0171 #define EMAC_WKUP_FFCRC01_1_MASK                  0xffff0000
0172 #define EMAC_WKUP_FFCRC01_1_SHIFT                         16
0173 #define EMAC_WKUP_FFCRC01_0_MASK                  0x0000ffff
0174 #define EMAC_WKUP_FFCRC01_0_SHIFT                          0
0175 
0176 #define EMAC_WKUP_FFCRC23_3_MASK                  0xffff0000
0177 #define EMAC_WKUP_FFCRC23_3_SHIFT                         16
0178 #define EMAC_WKUP_FFCRC23_2_MASK                  0x0000ffff
0179 #define EMAC_WKUP_FFCRC23_2_SHIFT                          0
0180 
0181 #define EMAC_SYSCTL_MDCDIV_MASK                   0x00003f00
0182 #define EMAC_SYSCTL_MDCDIV_SHIFT                           8
0183 #define EMAC_SYSCTL_TXDWA                         0x00000010
0184 #define EMAC_SYSCTL_RXCKS                         0x00000004
0185 #define EMAC_SYSCTL_RXDWA                         0x00000002
0186 #define EMAC_SYSCTL_PHYIE                         0x00000001
0187 
0188 #define EMAC_SYSTAT_STMDONE                       0x00000080
0189 #define EMAC_SYSTAT_TXDMAERR                      0x00000040
0190 #define EMAC_SYSTAT_RXDMAERR                      0x00000020
0191 #define EMAC_SYSTAT_WAKEDET                       0x00000010
0192 #define EMAC_SYSTAT_TXFSINT                       0x00000008
0193 #define EMAC_SYSTAT_RXFSINT                       0x00000004
0194 #define EMAC_SYSTAT_MMCINT                        0x00000002
0195 #define EMAC_SYSTAT_PHYINT                        0x00000001
0196 
0197 #define EMAC_RX_STAT_RX_ACCEPT                    0x80000000
0198 #define EMAC_RX_STAT_RX_VLAN2                     0x40000000
0199 #define EMAC_RX_STAT_RX_VLAN1                     0x20000000
0200 #define EMAC_RX_STAT_RX_TYPE                      0x10000000
0201 #define EMAC_RX_STAT_RX_UCTL                      0x08000000
0202 #define EMAC_RX_STAT_RX_CTL                       0x04000000
0203 #define EMAC_RX_STAT_RX_BROAD_MULTI_MASK          0x03000000
0204 #define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL       0x03000000
0205 #define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST     0x02000000
0206 #define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP         0x01000000
0207 #define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST       0x00000000
0208 #define EMAC_RX_STAT_RX_RANGE                     0x00800000
0209 #define EMAC_RX_STAT_RX_LATE                      0x00400000
0210 #define EMAC_RX_STAT_RX_PHY                       0x00200000
0211 #define EMAC_RX_STAT_RX_DMAO                      0x00100000
0212 #define EMAC_RX_STAT_RX_ADDR                      0x00080000
0213 #define EMAC_RX_STAT_RX_FRAG                      0x00040000
0214 #define EMAC_RX_STAT_RX_LEN                       0x00020000
0215 #define EMAC_RX_STAT_RX_CRC                       0x00010000
0216 #define EMAC_RX_STAT_RX_ALIGN                     0x00008000
0217 #define EMAC_RX_STAT_RX_LONG                      0x00004000
0218 #define EMAC_RX_STAT_RX_OK                        0x00002000
0219 #define EMAC_RX_STAT_RX_COMP                      0x00001000
0220 #define EMAC_RX_STAT_RX_FRLEN_MASK                0x000007ff
0221 #define EMAC_RX_STAT_RX_FRLEN_SHIFT                        0
0222 
0223 #define EMAC_RX_STKY_RX_ACCEPT                    0x80000000
0224 #define EMAC_RX_STKY_RX_VLAN2                     0x40000000
0225 #define EMAC_RX_STKY_RX_VLAN1                     0x20000000
0226 #define EMAC_RX_STKY_RX_TYPE                      0x10000000
0227 #define EMAC_RX_STKY_RX_UCTL                      0x08000000
0228 #define EMAC_RX_STKY_RX_CTL                       0x04000000
0229 #define EMAC_RX_STKY_RX_BROAD                     0x02000000
0230 #define EMAC_RX_STKY_RX_MULTI                     0x01000000
0231 #define EMAC_RX_STKY_RX_RANGE                     0x00800000
0232 #define EMAC_RX_STKY_RX_LATE                      0x00400000
0233 #define EMAC_RX_STKY_RX_PHY                       0x00200000
0234 #define EMAC_RX_STKY_RX_DMAO                      0x00100000
0235 #define EMAC_RX_STKY_RX_ADDR                      0x00080000
0236 #define EMAC_RX_STKY_RX_FRAG                      0x00040000
0237 #define EMAC_RX_STKY_RX_LEN                       0x00020000
0238 #define EMAC_RX_STKY_RX_CRC                       0x00010000
0239 #define EMAC_RX_STKY_RX_ALIGN                     0x00008000
0240 #define EMAC_RX_STKY_RX_LONG                      0x00004000
0241 #define EMAC_RX_STKY_RX_OK                        0x00002000
0242 #define EMAC_RX_STKY_RX_COMP                      0x00001000
0243 
0244 #define EMAC_RX_IRQE_RX_ACCEPT                    0x80000000
0245 #define EMAC_RX_IRQE_RX_VLAN2                     0x40000000
0246 #define EMAC_RX_IRQE_RX_VLAN1                     0x20000000
0247 #define EMAC_RX_IRQE_RX_TYPE                      0x10000000
0248 #define EMAC_RX_IRQE_RX_UCTL                      0x08000000
0249 #define EMAC_RX_IRQE_RX_CTL                       0x04000000
0250 #define EMAC_RX_IRQE_RX_BROAD                     0x02000000
0251 #define EMAC_RX_IRQE_RX_MULTI                     0x01000000
0252 #define EMAC_RX_IRQE_RX_RANGE                     0x00800000
0253 #define EMAC_RX_IRQE_RX_LATE                      0x00400000
0254 #define EMAC_RX_IRQE_RX_PHY                       0x00200000
0255 #define EMAC_RX_IRQE_RX_DMAO                      0x00100000
0256 #define EMAC_RX_IRQE_RX_ADDR                      0x00080000
0257 #define EMAC_RX_IRQE_RX_FRAG                      0x00040000
0258 #define EMAC_RX_IRQE_RX_LEN                       0x00020000
0259 #define EMAC_RX_IRQE_RX_CRC                       0x00010000
0260 #define EMAC_RX_IRQE_RX_ALIGN                     0x00008000
0261 #define EMAC_RX_IRQE_RX_LONG                      0x00004000
0262 #define EMAC_RX_IRQE_RX_OK                        0x00002000
0263 #define EMAC_RX_IRQE_RX_COMP                      0x00001000
0264 
0265 #define EMAC_TX_STAT_TX_FRLEN_MASK                0x07ff0000
0266 #define EMAC_TX_STAT_TX_FRLEN_SHIFT                       16
0267 #define EMAC_TX_STAT_TX_RETRY                     0x00008000
0268 #define EMAC_TX_STAT_TX_LOSS                      0x00004000
0269 #define EMAC_TX_STAT_TX_CRS                       0x00002000
0270 #define EMAC_TX_STAT_TX_DEFER                     0x00001000
0271 #define EMAC_TX_STAT_TX_CCNT_MASK                 0x00000f00
0272 #define EMAC_TX_STAT_TX_CCNT_SHIFT                         8
0273 #define EMAC_TX_STAT_TX_MULTI_BROAD_MASK          0x000000c0
0274 #define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL       0x000000c0
0275 #define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP         0x00000080
0276 #define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST     0x00000040
0277 #define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST       0x00000000
0278 #define EMAC_TX_STAT_TX_EDEFER                    0x00000020
0279 #define EMAC_TX_STAT_TX_DMAU                      0x00000010
0280 #define EMAC_TX_STAT_TX_LATE                      0x00000008
0281 #define EMAC_TX_STAT_TX_ECOLL                     0x00000004
0282 #define EMAC_TX_STAT_TX_OK                        0x00000002
0283 #define EMAC_TX_STAT_TX_COMP                      0x00000001
0284 
0285 #define EMAC_TX_STKY_TX_RETRY                     0x00008000
0286 #define EMAC_TX_STKY_TX_LOSS                      0x00004000
0287 #define EMAC_TX_STKY_TX_CRS                       0x00002000
0288 #define EMAC_TX_STKY_TX_DEFER                     0x00001000
0289 #define EMAC_TX_STKY_TX_CCNT_MASK                 0x00000f00
0290 #define EMAC_TX_STKY_TX_CCNT_SHIFT                         8
0291 #define EMAC_TX_STKY_TX_MULTI                     0x00000080
0292 #define EMAC_TX_STKY_TX_BROAD                     0x00000040
0293 #define EMAC_TX_STKY_TX_EDEFER                    0x00000020
0294 #define EMAC_TX_STKY_TX_DMAU                      0x00000010
0295 #define EMAC_TX_STKY_TX_LATE                      0x00000008
0296 #define EMAC_TX_STAT_TX_ECOLL                     0x00000004
0297 #define EMAC_TX_STAT_TX_OK                        0x00000002
0298 #define EMAC_TX_STAT_TX_COMP                      0x00000001
0299 
0300 #define EMAC_TX_IRQE_TX_RETRY                     0x00008000
0301 #define EMAC_TX_IRQE_TX_LOSS                      0x00004000
0302 #define EMAC_TX_IRQE_TX_CRS                       0x00002000
0303 #define EMAC_TX_IRQE_TX_DEFER                     0x00001000
0304 #define EMAC_TX_IRQE_TX_CCNT_MASK                 0x00000f00
0305 #define EMAC_TX_IRQE_TX_CCNT_SHIFT                         8
0306 #define EMAC_TX_IRQE_TX_MULTI                     0x00000080
0307 #define EMAC_TX_IRQE_TX_BROAD                     0x00000040
0308 #define EMAC_TX_IRQE_TX_EDEFER                    0x00000020
0309 #define EMAC_TX_IRQE_TX_DMAU                      0x00000010
0310 #define EMAC_TX_IRQE_TX_LATE                      0x00000008
0311 #define EMAC_TX_IRQE_TX_ECOLL                     0x00000004
0312 #define EMAC_TX_IRQE_TX_OK                        0x00000002
0313 #define EMAC_TX_IRQE_TX_COMP                      0x00000001
0314 
0315 #define EMAC_MMC_RIRQS_RX_GE1024_CNT              0x00800000
0316 #define EMAC_MMC_RIRQS_RX_LT1024_CNT              0x00400000
0317 #define EMAC_MMC_RIRQS_RX_LT512_CNT               0x00200000
0318 #define EMAC_MMC_RIRQS_RX_LT256_CNT               0x00100000
0319 #define EMAC_MMC_RIRQS_RX_LT128_CNT               0x00080000
0320 #define EMAC_MMC_RIRQS_RX_EQ64_CNT                0x00040000
0321 #define EMAC_MMC_RIRQS_RX_SHORT_CNT               0x00020000
0322 #define EMAC_MMC_RIRQS_RX_TYPED_CNT               0x00010000
0323 #define EMAC_MMC_RIRQS_RX_ALLO_CNT                0x00008000
0324 #define EMAC_MMC_RIRQS_RX_ALLF_CNT                0x00004000
0325 #define EMAC_MMC_RIRQS_RX_PAUSE_CNT               0x00002000
0326 #define EMAC_MMC_RIRQS_RX_OPCODE_CNT              0x00001000
0327 #define EMAC_MMC_RIRQS_RX_MACCTL_CNT              0x00000800
0328 #define EMAC_MMC_RIRQS_RX_LONG_CNT                0x00000400
0329 #define EMAC_MMC_RIRQS_RX_ORL_CNT                 0x00000200
0330 #define EMAC_MMC_RIRQS_RX_IRL_CNT                 0x00000100
0331 #define EMAC_MMC_RIRQS_RX_BROAD_CNT               0x00000080
0332 #define EMAC_MMC_RIRQS_RX_MULTI_CNT               0x00000040
0333 #define EMAC_MMC_RIRQS_RX_UNI_CNT                 0x00000020
0334 #define EMAC_MMC_RIRQS_RX_LOST_CNT                0x00000010
0335 #define EMAC_MMC_RIRQS_RX_OCTET_CNT               0x00000008
0336 #define EMAC_MMC_RIRQS_RX_ALIGN_CNT               0x00000004
0337 #define EMAC_MMC_RIRQS_RX_FCS_CNT                 0x00000002
0338 #define EMAC_MMC_RIRQS_RX_OK_CNT                  0x00000001
0339 
0340 #define EMAC_MMC_RIRQE_RX_GE1024_CNT              0x00800000
0341 #define EMAC_MMC_RIRQE_RX_LT1024_CNT              0x00400000
0342 #define EMAC_MMC_RIRQE_RX_LT512_CNT               0x00200000
0343 #define EMAC_MMC_RIRQE_RX_LT256_CNT               0x00100000
0344 #define EMAC_MMC_RIRQE_RX_LT128_CNT               0x00080000
0345 #define EMAC_MMC_RIRQE_RX_EQ64_CNT                0x00040000
0346 #define EMAC_MMC_RIRQE_RX_SHORT_CNT               0x00020000
0347 #define EMAC_MMC_RIRQE_RX_TYPED_CNT               0x00010000
0348 #define EMAC_MMC_RIRQE_RX_ALLO_CNT                0x00008000
0349 #define EMAC_MMC_RIRQE_RX_ALLF_CNT                0x00004000
0350 #define EMAC_MMC_RIRQE_RX_PAUSE_CNT               0x00002000
0351 #define EMAC_MMC_RIRQE_RX_OPCODE_CNT              0x00001000
0352 #define EMAC_MMC_RIRQE_RX_MACCTL_CNT              0x00000800
0353 #define EMAC_MMC_RIRQE_RX_LONG_CNT                0x00000400
0354 #define EMAC_MMC_RIRQE_RX_ORL_CNT                 0x00000200
0355 #define EMAC_MMC_RIRQE_RX_IRL_CNT                 0x00000100
0356 #define EMAC_MMC_RIRQE_RX_BROAD_CNT               0x00000080
0357 #define EMAC_MMC_RIRQE_RX_MULTI_CNT               0x00000040
0358 #define EMAC_MMC_RIRQE_RX_UNI_CNT                 0x00000020
0359 #define EMAC_MMC_RIRQE_RX_LOST_CNT                0x00000010
0360 #define EMAC_MMC_RIRQE_RX_OCTET_CNT               0x00000008
0361 #define EMAC_MMC_RIRQE_RX_ALIGN_CNT               0x00000004
0362 #define EMAC_MMC_RIRQE_RX_FCS_CNT                 0x00000002
0363 #define EMAC_MMC_RIRQE_RX_OK_CNT                  0x00000001
0364 
0365 #define EMAC_MMC_TIRQS_TX_ABORT_CNT               0x00400000
0366 #define EMAC_MMC_TIRQS_TX_GE1024_CNT              0x00200000
0367 #define EMAC_MMC_TIRQS_TX_LT1024_CNT              0x00100000
0368 #define EMAC_MMC_TIRQS_TX_LT512_CNT               0x00080000
0369 #define EMAC_MMC_TIRQS_TX_LT256_CNT               0x00040000
0370 #define EMAC_MMC_TIRQS_TX_LT128_CNT               0x00020000
0371 #define EMAC_MMC_TIRQS_TX_EQ64_CNT                0x00010000
0372 #define EMAC_MMC_TIRQS_TX_ALLO_CNT                0x00008000
0373 #define EMAC_MMC_TIRQS_TX_ALLF_CNT                0x00004000
0374 #define EMAC_MMC_TIRQS_TX_MACCTL_CNT              0x00002000
0375 #define EMAC_MMC_TIRQS_TX_EXDEF_CNT               0x00001000
0376 #define EMAC_MMC_TIRQS_TX_BROAD_CNT               0x00000800
0377 #define EMAC_MMC_TIRQS_TX_MULTI_CNT               0x00000400
0378 #define EMAC_MMC_TIRQS_TX_UNI_CNT                 0x00000200
0379 #define EMAC_MMC_TIRQS_TX_CRS_CNT                 0x00000100
0380 #define EMAC_MMC_TIRQS_TX_LOST_CNT                0x00000080
0381 #define EMAC_MMC_TIRQS_TX_ABORTC_CNT              0x00000040
0382 #define EMAC_MMC_TIRQS_TX_LATE_CNT                0x00000020
0383 #define EMAC_MMC_TIRQS_TX_DEFER_CNT               0x00000010
0384 #define EMAC_MMC_TIRQS_TX_OCTET_CNT               0x00000008
0385 #define EMAC_MMC_TIRQS_TX_MCOLL_CNT               0x00000004
0386 #define EMAC_MMC_TIRQS_TX_SCOLL_CNT               0x00000002
0387 #define EMAC_MMC_TIRQS_TX_OK_CNT                  0x00000001
0388 
0389 #define EMAC_MMC_TIRQE_TX_ABORT_CNT               0x00400000
0390 #define EMAC_MMC_TIRQE_TX_GE1024_CNT              0x00200000
0391 #define EMAC_MMC_TIRQE_TX_LT1024_CNT              0x00100000
0392 #define EMAC_MMC_TIRQE_TX_LT512_CNT               0x00080000
0393 #define EMAC_MMC_TIRQE_TX_LT256_CNT               0x00040000
0394 #define EMAC_MMC_TIRQE_TX_LT128_CNT               0x00020000
0395 #define EMAC_MMC_TIRQE_TX_EQ64_CNT                0x00010000
0396 #define EMAC_MMC_TIRQE_TX_ALLO_CNT                0x00008000
0397 #define EMAC_MMC_TIRQE_TX_ALLF_CNT                0x00004000
0398 #define EMAC_MMC_TIRQE_TX_MACCTL_CNT              0x00002000
0399 #define EMAC_MMC_TIRQE_TX_EXDEF_CNT               0x00001000
0400 #define EMAC_MMC_TIRQE_TX_BROAD_CNT               0x00000800
0401 #define EMAC_MMC_TIRQE_TX_MULTI_CNT               0x00000400
0402 #define EMAC_MMC_TIRQE_TX_UNI_CNT                 0x00000200
0403 #define EMAC_MMC_TIRQE_TX_CRS_CNT                 0x00000100
0404 #define EMAC_MMC_TIRQE_TX_LOST_CNT                0x00000080
0405 #define EMAC_MMC_TIRQE_TX_ABORTC_CNT              0x00000040
0406 #define EMAC_MMC_TIRQE_TX_LATE_CNT                0x00000020
0407 #define EMAC_MMC_TIRQE_TX_DEFER_CNT               0x00000010
0408 #define EMAC_MMC_TIRQE_TX_OCTET_CNT               0x00000008
0409 #define EMAC_MMC_TIRQE_TX_MCOLL_CNT               0x00000004
0410 #define EMAC_MMC_TIRQE_TX_SCOLL_CNT               0x00000002
0411 #define EMAC_MMC_TIRQE_TX_OK_CNT                  0x00000001
0412 
0413 #define EMAC_MMC_CTL_MMCE                         0x00000008
0414 #define EMAC_MMC_CTL_CCOR                         0x00000004
0415 #define EMAC_MMC_CTL_CROLL                        0x00000002
0416 #define EMAC_MMC_CTL_RSTC                         0x00000001
0417 
0418 
0419 #endif /* _ethernetRegs_h_ */