File indexing completed on 2025-05-11 08:23:40
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0011 #ifndef _bf533_h_
0012 #define _bf533_h_
0013
0014
0015
0016 #define SIC_BASE_ADDRESS 0xffc00100
0017 #define WDOG_BASE_ADDRESS 0xffc00200
0018 #define RTC_BASE_ADDRESS 0xffc00300
0019 #define UART0_BASE_ADDRESS 0xffc00400
0020 #define SPI_BASE_ADDRESS 0xffc00500
0021 #define TIMER_BASE_ADDRESS 0xffc00600
0022 #define TIMER_CHANNELS 3
0023 #define TIMER_PITCH 0x10
0024 #define TIMER0_BASE_ADDRESS 0xffc00600
0025 #define TIMER1_BASE_ADDRESS 0xffc00610
0026 #define TIMER2_BASE_ADDRESS 0xffc00620
0027 #define TIMER_ENABLE 0xffc00640
0028 #define TIMER_DISABLE 0xffc00644
0029 #define TIMER_STATUS 0xffc00648
0030 #define PORTFIO_BASE_ADDRESS 0xffc00700
0031 #define SPORT0_BASE_ADDRESS 0xffc00800
0032 #define SPORT1_BASE_ADDRESS 0xffc00900
0033 #define EBIU_BASE_ADDRESS 0xffc00a00
0034 #define DMA_TC_PER 0xffc00b0c
0035 #define DMA_TC_CNT 0xffc00b10
0036 #define DMA_BASE_ADDRESS 0xffc00c00
0037 #define DMA_CHANNELS 8
0038 #define DMA_PITCH 0x40
0039 #define DMA0_BASE_ADDRESS 0xffc00c00
0040 #define DMA1_BASE_ADDRESS 0xffc00c40
0041 #define DMA2_BASE_ADDRESS 0xffc00c80
0042 #define DMA3_BASE_ADDRESS 0xffc00cc0
0043 #define DMA4_BASE_ADDRESS 0xffc00d00
0044 #define DMA5_BASE_ADDRESS 0xffc00d40
0045 #define DMA6_BASE_ADDRESS 0xffc00d80
0046 #define DMA7_BASE_ADDRESS 0xffc00dc0
0047 #define MDMA_BASE_ADDRESS 0xffc00e00
0048 #define MDMA_CHANNELS 2
0049 #define MDMA_D_S 0x40
0050 #define MDMA_PITCH 0x80
0051 #define MDMA0D_BASE_ADDRESS 0xffc00e00
0052 #define MDMA0S_BASE_ADDRESS 0xffc00e40
0053 #define MDMA1D_BASE_ADDRESS 0xffc00e80
0054 #define MDMA1S_BASE_ADDRESS 0xffc00ec0
0055 #define PPI_BASE_ADDRESS 0xffc01000
0056
0057
0058
0059
0060 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800
0061 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11
0062 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700
0063 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8
0064 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0
0065 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4
0066 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f
0067 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0
0068
0069 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800
0070 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11
0071 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700
0072 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8
0073 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0
0074 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4
0075 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f
0076 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0
0077
0078 #define TIMER_ENABLE_TIMEN2 0x0004
0079 #define TIMER_ENABLE_TIMEN1 0x0002
0080 #define TIMER_ENABLE_TIMEN0 0x0001
0081
0082 #define TIMER_DISABLE_TIMDIS2 0x0004
0083 #define TIMER_DISABLE_TIMDIS1 0x0002
0084 #define TIMER_DISABLE_TIMDIS0 0x0001
0085
0086 #define TIMER_STATUS_TRUN2 0x00004000
0087 #define TIMER_STATUS_TRUN1 0x00002000
0088 #define TIMER_STATUS_TRUN0 0x00001000
0089 #define TIMER_STATUS_TOVF_ERR2 0x00000040
0090 #define TIMER_STATUS_TOVF_ERR1 0x00000020
0091 #define TIMER_STATUS_TOVF_ERR0 0x00000010
0092 #define TIMER_STATUS_TIMIL2 0x00000004
0093 #define TIMER_STATUS_TIMIL1 0x00000002
0094 #define TIMER_STATUS_TIMIL0 0x00000001
0095
0096
0097
0098 #define CEC_EMULATION_VECTOR 0
0099 #define CEC_RESET_VECTOR 1
0100 #define CEC_NMI_VECTOR 2
0101 #define CEC_EXCEPTIONS_VECTOR 3
0102 #define CEC_HARDWARE_ERROR_VECTOR 5
0103 #define CEC_CORE_TIMER_VECTOR 6
0104 #define CEC_INTERRUPT_BASE_VECTOR 7
0105 #define CEC_INTERRUPT_COUNT 9
0106
0107
0108
0109
0110 #define SIC_IAR_COUNT 3
0111
0112 #define SIC_PLL_WAKEUP_VECTOR 0
0113 #define SIC_DMA_ERROR_VECTOR 1
0114 #define SIC_PPI_ERROR_VECTOR 2
0115 #define SIC_SPORT0_ERROR_VECTOR 3
0116 #define SIC_SPORT1_ERROR_VECTOR 4
0117 #define SIC_SPI_ERROR_VECTOR 5
0118 #define SIC_UART0_ERROR_VECTOR 6
0119 #define SIC_RTC_VECTOR 7
0120 #define SIC_DMA0_PPI_VECTOR 8
0121 #define SIC_DMA1_SPORT0_RX_VECTOR 9
0122 #define SIC_DMA2_SPORT0_TX_VECTOR 10
0123 #define SIC_DMA3_SPORT1_RX_VECTOR 11
0124 #define SIC_DMA4_SPORT1_TX_VECTOR 12
0125 #define SIC_DMA5_SPI_VECTOR 13
0126 #define SIC_DMA6_UART0_RX_VECTOR 14
0127 #define SIC_DMA7_UART0_TX_VECTOR 15
0128 #define SIC_TIMER0_VECTOR 16
0129 #define SIC_TIMER1_VECTOR 17
0130 #define SIC_TIMER2_VECTOR 18
0131 #define SIC_MDMA0_VECTOR 21
0132 #define SIC_MDMA1_VECTOR 22
0133 #define SIC_WATCHDOG_VECTOR 23
0134
0135 #endif