include/bsp/interrupt.h

0001 /**
0002  *@file
0003  *
0004  *@brief
0005  *  - This file implements interrupt dispatcher. The init code is taken from
0006  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
0007  *  registers some portion is written twice.
0008  *
0009  * Target:   TLL6527v1-0
0010  * Compiler:
0011  *
0012  * COPYRIGHT (c) 2010 by ECE Northeastern University.
0013  *
0014  * The license and distribution terms for this file may be
0015  * found in the file LICENSE in this distribution or at
0016  * http://www.rtems.org/license
0017  *
0018  * @author Rohan Kangralkar, ECE, Northeastern University
0019  *         (kangralkar.r@husky.neu.edu)
0020  *
0021  * LastChange:
0022  */
0023
0024 #ifndef _BFIN_INTERRUPT_H_
0025 #define _BFIN_INTERRUPT_H_
0026
0027
0028 #ifdef __cplusplus
0029 extern "C" {
0030 #endif
0031
0032 /** The type of interrupts handled by the SIC
0033  */
0034 typedef enum {
0035     IRQ_PLL_WAKEUP_INTERRUPT,                 /* 0 */
0036     IRQ_DMA_ERROR_0,                          /* 1 */
0037     IRQ_DMAR0_BLOCK_INTERRUPT,                /* 2 */
0038     IRQ_DMAR1_BLOCK_INTERRUPT,                /* 3 */
0039     IRQ_DMAR0_OVERFLOW_ERROR,                 /* 4 */
0040     IRQ_DMAR1_OVERFLOW_ERROR,                 /* 5 */
0041     IRQ_PPI_STATUS,                           /* 6 */
0042     IRQ_MAC_STATUS,                           /* 7 */
0043     IRQ_SPORT0_STATUS,                        /* 8 */
0044     IRQ_SPORT1_STATUS,                        /* 9 */
0045     IRQ_RESERVED_10,                          /* 10 */
0046     IRQ_RESERVED_11,                          /* 11 */
0047     IRQ_UART0_STATUS,                         /* 12 */
0048     IRQ_UART1_STATUS,                         /* 13 */
0049     IRQ_REAL_TIME_CLOCK,                      /* 14 */
0050     IRQ_DMA0_PPI_NFC,                         /* 15 */
0051     IRQ_DMA3_SPORT0_RX,                       /* 16 */
0052     IRQ_DMA4_SPORT0_TX,                       /* 17 */
0053     IRQ_DMA5_SPORT1_RX,                       /* 18 */
0054     IRQ_DMA6_SPORT1_TX,                       /* 19 */
0055     IRQ_TWI_INTERRUPT,                        /* 20 */
0056     IRQ_DMA7_SPI,                             /* 21 */
0057     IRQ_DMA8_UART0_RX,                        /* 22 */
0058     IRQ_DMA9_UART0_TX,                        /* 23 */
0059     IRQ_DMA10_UART1_RX,                       /* 24 */
0060     IRQ_DMA11_UART1_TX,                       /* 25 */
0061     IRQ_OTP,                                  /* 26 */
0062     IRQ_GP_COUNTER,                           /* 27 */
0063     IRQ_DMA1_MAC_RX_HOSTDP,                   /* 28 */
0064     IRQ_PORT_H_INTERRUPT_A,                   /* 29 */
0065     IRQ_DMA2_MAC_TX_NFC,                      /* 30 */
0066     IRQ_PORT_H_INTERRUPT_B,                   /* 31 */
0067     SIC_ISR0_MAX,                             /* 32 ***/
0068     IRQ_TIMER0 = SIC_ISR0_MAX,                /* 32 */
0069     IRQ_TIMER1,                               /* 33 */
0070     IRQ_TIMER2,                               /* 34 */
0071     IRQ_TIMER3,                               /* 35 */
0072     IRQ_TIMER4,                               /* 36 */
0073     IRQ_TIMER5,                               /* 37 */
0074     IRQ_TIMER6,                               /* 38 */
0075     IRQ_TIMER7,                               /* 39 */
0076     IRQ_PORT_G_INTERRUPT_A,                   /* 40 */
0077     IRQ_PORT_G_INTERRUPT_B,                   /* 41 */
0078     IRQ_MDMA0_STREAM_0_INTERRUPT,             /* 42 */
0079     IRQ_MDMA1_STREAM_0_INTERRUPT,             /* 43 */
0080     IRQ_SOFTWARE_WATCHDOG_INTERRUPT,          /* 44 */
0081     IRQ_PORT_F_INTERRUPT_A,                   /* 45 */
0082     IRQ_PORT_F_INTERRUPT_B,                   /* 46 */
0083     IRQ_SPI_STATUS,                           /* 47 */
0084     IRQ_NFC_STATUS,                           /* 48 */
0085     IRQ_HOSTDP_STATUS,                        /* 49 */
0086     IRQ_HOREAD_DONE_INTERRUPT,                /* 50 */
0087     IRQ_RESERVED_19,                          /* 51 */
0088     IRQ_USB_INT0_INTERRUPT,                   /* 52 */
0089     IRQ_USB_INT1_INTERRUPT,                   /* 53 */
0090     IRQ_USB_INT2_INTERRUPT,                   /* 54 */
0091     IRQ_USB_DMAINT,                           /* 55 */
0092     IRQ_MAX,                                  /* 56 */
0093 } e_isr_t;
0094
0095
0096
0097
0098 /* source is the source to the SIC (the bit number in SIC_ISR).  isr is
0099    the function that will be called when the interrupt is active. */
0100 typedef struct bfin_isr_s {
0101 #if INTERRUPT_USE_TABLE
0102   e_isr_t source;
0103   void (*pFunc)(void *arg);
0104   void *pArg;
0105   int priority; /** not used */
0106 #else
0107   int source;
0108   void (*isr)(void *arg);
0109   void *_arg;
0110   /* the following are for internal use only */
0111   uint32_t mask0;
0112   uint32_t mask1;
0113   uint32_t vector;
0114   struct bfin_isr_s *next;
0115 #endif
0116 } bfin_isr_t;
0117
0118 /**
0119  * This routine registers a new ISR. It will write a new entry to the IVT table
0120  * @param isr contains a callback function and source
0121  * @return rtems status code
0122  */
0123 rtems_status_code bfin_interrupt_register(bfin_isr_t *isr);
0124
0125 /**
0126  * This function unregisters a registered interrupt handler.
0127  * @param isr
0128  */
0129 rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr);
0130
0131 /**
0132  * blackfin interrupt initialization routine. It initializes the bfin ISR
0133  * dispatcher. It will also create SIC CEC map which will be used for
0134  * identifying the ISR.
0135  */
0136 void bfin_interrupt_init(void);
0137
0138
0139 #ifdef __cplusplus
0140 }
0141 #endif
0142
0143 #endif /* _BFIN_INTERRUPT_H_ */
0144