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File indexing completed on 2025-05-11 08:23:40

0001 /**
0002  *@file
0003  *
0004  *@brief
0005  *  - This file provides the register address for the 52X model. The file is
0006  *  based on the 533 implementation with some addition to support 52X range of
0007  *  processors.
0008  *
0009  * Target:   TLL6527v1-0
0010  * Compiler:
0011  *
0012  * COPYRIGHT (c) 2010 by ECE Northeastern University.
0013  *
0014  * The license and distribution terms for this file may be
0015  * found in the file LICENSE in this distribution or at
0016  * http://www.rtems.org/license
0017  *
0018  * @author Rohan Kangralkar, ECE, Northeastern University
0019  *         (kangralkar.r@husky.neu.edu)
0020  *
0021  * LastChange:
0022  */
0023 
0024 #ifndef _BF52X_H_
0025 #define _BF52X_H_
0026 
0027 /* register (or register block) addresses */
0028 
0029 #define SIC_BASE_ADDRESS                          0xffc00100
0030 #define WDOG_BASE_ADDRESS                         0xffc00200
0031 #define RTC_BASE_ADDRESS                          0xffc00300
0032 #define UART0_BASE_ADDRESS                        0xffc00400
0033 #define UART1_BASE_ADDRESS                        0xffc02000
0034 #define SPI_BASE_ADDRESS                          0xffc00500
0035 #define TIMER_BASE_ADDRESS                        0xffc00600
0036 #define TIMER_CHANNELS                                     3
0037 #define TIMER_PITCH                                     0x10
0038 #define TIMER0_BASE_ADDRESS                       0xffc00600
0039 #define TIMER1_BASE_ADDRESS                       0xffc00610
0040 #define TIMER2_BASE_ADDRESS                       0xffc00620
0041 #define TIMER_ENABLE                              0xffc00640
0042 #define TIMER_DISABLE                             0xffc00644
0043 #define TIMER_STATUS                              0xffc00648
0044 #define PORTFIO_BASE_ADDRESS                      0xffc00700
0045 #define SPORT0_BASE_ADDRESS                       0xffc00800
0046 #define SPORT1_BASE_ADDRESS                       0xffc00900
0047 #define EBIU_BASE_ADDRESS                         0xffc00a00
0048 #define DMA_TC_PER                                0xffc00b0c
0049 #define DMA_TC_CNT                                0xffc00b10
0050 #define DMA_BASE_ADDRESS                          0xffc00c00
0051 #define DMA_CHANNELS                                       8
0052 #define DMA_PITCH                                       0x40
0053 #define DMA0_BASE_ADDRESS                         0xffc00c00
0054 #define DMA1_BASE_ADDRESS                         0xffc00c40
0055 #define DMA2_BASE_ADDRESS                         0xffc00c80
0056 #define DMA3_BASE_ADDRESS                         0xffc00cc0
0057 #define DMA4_BASE_ADDRESS                         0xffc00d00
0058 #define DMA5_BASE_ADDRESS                         0xffc00d40
0059 #define DMA6_BASE_ADDRESS                         0xffc00d80
0060 #define DMA7_BASE_ADDRESS                         0xffc00dc0
0061 #define DMA8_BASE_ADDRESS                         0xffc00e00
0062 #define DMA9_BASE_ADDRESS                         0xffc00e40
0063 #define DMA10_BASE_ADDRESS                        0xffc00e80
0064 #define DMA11_BASE_ADDRESS                        0xffc00ec0
0065 #define MDMA_BASE_ADDRESS                         0xffc00e00
0066 #define MDMA_CHANNELS                                      2
0067 #define MDMA_D_S                                        0x40
0068 #define MDMA_PITCH                                      0x80
0069 #define MDMA0D_BASE_ADDRESS                       0xffc00e00
0070 #define MDMA0S_BASE_ADDRESS                       0xffc00e40
0071 #define MDMA1D_BASE_ADDRESS                       0xffc00e80
0072 #define MDMA1S_BASE_ADDRESS                       0xffc00ec0
0073 #define PPI_BASE_ADDRESS                          0xffc01000
0074 
0075 
0076 /* register fields */
0077 
0078 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
0079 #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
0080 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
0081 #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
0082 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
0083 #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
0084 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
0085 #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
0086 
0087 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
0088 #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
0089 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
0090 #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
0091 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
0092 #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
0093 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
0094 #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
0095 
0096 #define TIMER_ENABLE_TIMEN2                           0x0004
0097 #define TIMER_ENABLE_TIMEN1                           0x0002
0098 #define TIMER_ENABLE_TIMEN0                           0x0001
0099 
0100 #define TIMER_DISABLE_TIMDIS2                         0x0004
0101 #define TIMER_DISABLE_TIMDIS1                         0x0002
0102 #define TIMER_DISABLE_TIMDIS0                         0x0001
0103 
0104 #define TIMER_STATUS_TRUN2                        0x00004000
0105 #define TIMER_STATUS_TRUN1                        0x00002000
0106 #define TIMER_STATUS_TRUN0                        0x00001000
0107 #define TIMER_STATUS_TOVF_ERR2                    0x00000040
0108 #define TIMER_STATUS_TOVF_ERR1                    0x00000020
0109 #define TIMER_STATUS_TOVF_ERR0                    0x00000010
0110 #define TIMER_STATUS_TIMIL2                       0x00000004
0111 #define TIMER_STATUS_TIMIL1                       0x00000002
0112 #define TIMER_STATUS_TIMIL0                       0x00000001
0113 
0114 /* Core Event Controller vectors */
0115 
0116 #define CEC_EMULATION_VECTOR                               0
0117 #define CEC_RESET_VECTOR                                   1
0118 #define CEC_NMI_VECTOR                                     2
0119 #define CEC_EXCEPTIONS_VECTOR                              3
0120 #define CEC_HARDWARE_ERROR_VECTOR                          5
0121 #define CEC_CORE_TIMER_VECTOR                              6
0122 #define CEC_INTERRUPT_BASE_VECTOR                          7
0123 #define CEC_INTERRUPT_COUNT                                9
0124 
0125 
0126 /* System Interrupt Controller vectors */
0127 
0128 #define SIC_IAR_COUNT                                      8
0129 
0130 #endif /* _BF52X_H_ */
0131