File indexing completed on 2025-05-11 08:23:40
0001 #include <libcpu/bf537.h>
0002 #include <libcpu/sicRegs.h>
0003 #include <libcpu/cecRegs.h>
0004 #include <libcpu/dmaRegs.h>
0005 #include <libcpu/coreTimerRegs.h>
0006
0007 #ifndef LO
0008 #define LO(con32) ((con32) & 0xFFFF)
0009 #endif
0010 #ifndef HI
0011 #define HI(con32) (((con32) >> 16) & 0xFFFF)
0012 #endif
0013
0014 .section .start
0015 .align 4
0016
0017 .global __start
0018 __start:
0019 cli r0;
0020
0021
0022 sp.h = __ISR_Stack_area_end;
0023 sp.l = __ISR_Stack_area_end;
0024
0025
0026 p0.h = HI(TCNTL);
0027 p0.l = LO(TCNTL);
0028 r0 = 0;
0029 [p0] = r0;
0030
0031
0032 p0.h = HI(SIC_IMASK);
0033 p0.l = LO(SIC_IMASK);
0034 [p0] = r0;
0035
0036
0037 p0.h = HI(CEC_ILAT);
0038 p0.l = LO(CEC_ILAT);
0039 r0 = 0xffff (z);
0040 [p0] = r0;
0041
0042
0043 p0.h = HI(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET);
0044 p0.l = LO(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET);
0045 p1 = DMA_PITCH;
0046 p2 = DMA_CHANNELS;
0047 r0 = ~DMA_CONFIG_DMAEN;
0048 lsetup(loop1,loop2) lc0 = p2;
0049 loop1: r1 = w[p0];
0050 r1 = r0 & r1;
0051 loop2: w[p0 ++ p1] = r1.l;
0052
0053
0054
0055 p0.h = start;
0056 p0.l = start;
0057 p1.h = HI(CEC_EVT15);
0058 p1.l = LO(CEC_EVT15);
0059
0060 [p1] = p0;
0061
0062 r0 = 0x8000 (z);
0063 sti r0;
0064
0065 raise 15;
0066
0067 p0.h = wait;
0068 p0.l = wait;
0069
0070 reti = p0;
0071 rti;
0072
0073
0074 wait:
0075 jump wait;
0076
0077 start:
0078 [--sp] = reti;
0079
0080
0081 cli r0;
0082
0083 p0.h = _bss_start;
0084 p0.l = _bss_start;
0085 p1.h = _end;
0086 p1.l = _end;
0087 r0 = p0;
0088 r1 = p1;
0089 r1 = r1 - r0;
0090 p1 = r1;
0091 r0 = 0;
0092
0093
0094 lsetup(loop3,loop4) lc0 = p1;
0095 loop3: b[p0] = r0;
0096 loop4: p0 +=1;
0097
0098 l0 = 0;
0099 l1 = 0;
0100 l2 = 0;
0101 l3 = 0;
0102 sp += -12;
0103
0104 p0.h = _boot_card;
0105 p0.l = _boot_card;
0106 call (p0);
0107 sp += 12;
0108
0109 .global _bsp_reset
0110 _bsp_reset:
0111 HLT
0112 p0.h = _exit;
0113 p0.l = _exit;
0114 jump (p0);
0115