bf537Stamp/start/bspstart.c

0001 /*  bspstart.c for bf537Stamp
0002  *
0003  *  This routine does the bulk of the system initialisation.
0004  */
0005
0006 /*
0007  *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
0008  *             written by Alain Schaefer <alain.schaefer@easc.ch>
0009  *                    and Antonio Giovanini <antonio@atos.com.br>
0010  *
0011  *  The license and distribution terms for this file may be
0012  *  found in the file LICENSE in this distribution or at
0013  *  http://www.rtems.org/license/LICENSE.
0014  */
0015
0016
0017 #include <bsp.h>
0018 #include <bsp/bootcard.h>
0019 #include <libcpu/bf537.h>
0020 #include <libcpu/ebiuRegs.h>
0021 #include <libcpu/gpioRegs.h>
0022 #include <libcpu/mmu.h>
0023 #include <libcpu/mmuRegs.h>
0024 #include <libcpu/interrupt.h>
0025 #include <rtems/sysinit.h>
0026
0027 static bfin_mmu_config_t mmuRegions = {
0028     /* instruction */
0029     {
0030         {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0031         {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0032         {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0033         {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0034         {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0035         {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0036         {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0037         {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0038         {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0039         {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0040         {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0041         {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0042         {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0043         {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
0044         {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
0045         {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
0046     },
0047     /* data */
0048     {
0049         {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0050         {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0051         {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0052         {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0053         {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0054         {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0055         {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0056         {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0057         {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0058         {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0059         {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0060         {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0061         {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0062         {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
0063         {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
0064         {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
0065     }
0066 };
0067
0068 static void initPLL(void);
0069 static void initEBIU(void);
0070 static void initGPIO(void);
0071
0072 RTEMS_SYSINIT_ITEM(
0073   bfin_interrupt_init,
0074   RTEMS_SYSINIT_BSP_PRE_DRIVERS,
0075   RTEMS_SYSINIT_ORDER_MIDDLE
0076 );
0077
0078 void bsp_start(void)
0079 {
0080   /* BSP Hardware Initialization*/
0081
0082   *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
0083   *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
0084   bfin_mmu_init(&mmuRegions);
0085   rtems_cache_enable_instruction();
0086   rtems_cache_enable_data();
0087
0088   Init_RTC();   /* Blackfin Real Time Clock initialization */
0089
0090   initPLL();   /* PLL initialization */
0091   initEBIU();  /* EBIU initialization */
0092   initGPIO();  /* GPIO initialization */
0093 }
0094
0095  /*
0096   * initPLL
0097   *
0098   * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON
0099   * See "../bf537Stamp/include/bsp.h" for more information.
0100   */
0101
0102 static void initPLL(void) {
0103
0104 #ifdef BISON
0105   unsigned int n;
0106
0107   /* Configure PLL registers */
0108   *((uint16_t*)PLL_LOCKCNT) = 0x1000;
0109   *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
0110   *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
0111
0112   /* Commands to set PLL values */
0113   __asm__ ("cli r0;");
0114   __asm__ ("idle;");
0115   __asm__ ("sti r0;");
0116
0117   /* Delay for PLL stabilization */
0118   for (n=0; n<200; n++) {}
0119 #endif
0120
0121 }
0122
0123  /*
0124   * initEBIU
0125   *
0126   * Configure extern memory
0127   */
0128
0129 static void initEBIU(void) {
0130
0131   /* by default the processor has priority over dma channels for access to
0132      external memory.  this has been seen to result in dma unerruns on
0133      ethernet transmit; it seems likely it could cause dma overruns on
0134      ethernet receive as well.  setting the following bit gives the dma
0135      channels priority over the cpu, fixing that problem.  unfortunately
0136      we don't have finer grain control than that; all dma channels now
0137      have priority over the cpu. */
0138   *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
0139
0140 #ifdef BISON
0141   /* Configure FLASH */
0142   *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
0143   *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
0144   *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
0145
0146   /* Configure SDRAM
0147   *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
0148   *((uint16_t*)EBIU_SDBCTL) = 0x0013;
0149   *((uint16_t*)EBIU_SDRRC)  = 0x0817;
0150   */
0151 #endif
0152 }
0153
0154  /*
0155   * initGPIO
0156   *
0157   * Enable LEDs port
0158   */
0159 static void initGPIO(void) {
0160 #if (!BFIN_ON_SKYEYE)
0161   *(uint16_t volatile *) PORT_MUX = 0;
0162
0163   /* port f bits 0, 1: uart0 tx, rx */
0164   /*        bits 2 - 5: buttons */
0165   /*        bits 6 - 11: leds */
0166   *(uint16_t volatile *) PORTF_FER = 0x0003;
0167   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
0168   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c;
0169   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
0170   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
0171   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
0172   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
0173   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
0174   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0;
0175
0176   *(uint16_t volatile *) PORTG_FER = 0x0000;
0177   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
0178   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
0179   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
0180   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
0181   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
0182   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
0183   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
0184   *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
0185
0186   /* port h bits 0 - 15: ethernet */
0187   *(uint16_t volatile *) PORTH_FER = 0xffff;
0188   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
0189   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
0190   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
0191   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
0192   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
0193   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
0194   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
0195   *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
0196 #endif
0197 }
0198
0199 /*
0200  * Helper Function to use the EzKits LEDS.
0201  * Can be used by the Application.
0202  */
0203 void setLEDs(uint8_t value) {
0204
0205   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) =
0206       (uint16_t) (~value & 0x3f) << 6;
0207   *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) =
0208       (uint16_t) (value & 0x3f) << 6;
0209 }
0210
0211 /*
0212  * Helper Function to use the EzKits LEDS
0213  */
0214 uint8_t getLEDs(void) {
0215   uint16_t r;
0216
0217   r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
0218   return (uint8_t) ((r >> 6) & 0x3f);
0219 }
0220
0221 uint8_t getButtons(void) {
0222   uint16_t r;
0223
0224   r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
0225
0226   return (uint8_t) ((r >> 2) & 0x0f);
0227 }
0228
0229