TLL6527M/start/bspstart.c

0001 /*  bspstart.c for TLL6527M
0002  *
0003  *  This routine does the bulk of the system initialization.
0004  */
0005
0006 /*
0007  * COPYRIGHT (c) 2010 by ECE Northeastern University.
0008  *
0009  * The license and distribution terms for this file may be
0010  * found in the file LICENSE in this distribution or at
0011  * http://www.rtems.org/license
0012  */
0013
0014 #include <bsp.h>
0015 #include <bsp/bootcard.h>
0016 #include <cplb.h>
0017 #include <bsp/interrupt.h>
0018 #include <libcpu/ebiuRegs.h>
0019 #include <rtems/sysinit.h>
0020
0021 const unsigned int dcplbs_table[16][2] = {
0022   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
0023   { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
0024   { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
0025   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
0026
0027   { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
0028   { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
0029   { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
0030   { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
0031
0032   { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0033   { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0034   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0035   { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0036   { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0037   { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
0038
0039   { 0xffffffff, 0xffffffff }/* end of section - termination */
0040 };
0041
0042
0043 const unsigned int _icplbs_table[16][2] = {
0044   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
0045   /* L1 Code */
0046   { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
0047   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
0048
0049   { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
0050   { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
0051   { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
0052   { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
0053
0054   { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0055   { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0056   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0057   { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0058   { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0059   { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
0060
0061   { 0xffffffff, 0xffffffff }/* end of section - termination */
0062 };
0063
0064 /*
0065  * Init_PLL
0066  *
0067  * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
0068  */
0069 static void Init_PLL (void)
0070 {
0071   unsigned short msel = 0;
0072   unsigned short ssel = 0;
0073
0074   msel = (unsigned short)( (float)CCLK/(float)CLKIN );
0075   ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
0076
0077   asm("cli r0;");
0078
0079   *((uint32_t*)SIC_IWR) = 0x1;
0080
0081   /* Configure PLL registers */
0082   *((uint16_t*)PLL_DIV) = ssel;
0083   msel = msel<<9;
0084   *((uint16_t*)PLL_CTL) = msel;
0085
0086   /* Commands to set PLL values */
0087   asm("idle;");
0088   asm("sti r0;");
0089 }
0090
0091 /*
0092  * Init_EBIU
0093  *
0094  * Configure extern memory
0095  */
0096 static void Init_EBIU (void)
0097 {
0098   /* Check if SDRAM is already enabled */
0099   if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
0100     asm("ssync;");
0101     /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
0102     *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
0103     *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
0104         EBIU_SDBCTL_EBE;
0105     *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
0106     asm("ssync;");
0107   } else {
0108     /* SDRAm is already programmed */
0109   }
0110 }
0111
0112 /*
0113  * Init_Flags
0114  *
0115  * Enable LEDs port
0116  */
0117 static void Init_Flags(void)
0118 {
0119   *((uint16_t*)PORTH_FER)    = 0x0;
0120   *((uint16_t*)PORTH_MUX)    = 0x0;
0121   *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
0122   *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
0123 }
0124
0125 RTEMS_SYSINIT_ITEM(
0126   bfin_interrupt_init,
0127   RTEMS_SYSINIT_BSP_PRE_DRIVERS,
0128   RTEMS_SYSINIT_ORDER_MIDDLE
0129 );
0130
0131 void bsp_start( void )
0132 {
0133   int i;
0134
0135   /* BSP Hardware Initialization*/
0136   Init_RTC();   /* Blackfin Real Time Clock initialization */
0137   Init_PLL();   /* PLL initialization */
0138   Init_EBIU();  /* EBIU initialization */
0139   Init_Flags(); /* GPIO initialization */
0140
0141   /*
0142    *  Allocate the memory for the RTEMS Work Space.  This can come from
0143    *  a variety of places: hard coded address, malloc'ed from outside
0144    *  RTEMS world (e.g. simulator or primitive memory manager), or (as
0145    *  typically done by stock BSPs) by subtracting the required amount
0146    *  of work space from the last physical address on the CPU board.
0147    */
0148   for (i=5;i<16;i++) {
0149     set_vector((rtems_isr_entry)bfin_null_isr, i, 1);
0150   }
0151
0152 }