xilinx-zynqmp/start/bspsmp.c

0001 /*
0002  * SPDX-License-Identifier: BSD-2-Clause
0003  *
0004  * Copyright (C) 2014 embedded brains GmbH & Co. KG
0005  *
0006  * Copyright (C) 2019 DornerWorks
0007  *
0008  * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
0009  *        and Josh Whitehead <josh.whitehead@dornerworks.com>
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions
0013  * are met:
0014  * 1. Redistributions of source code must retain the above copyright
0015  *    notice, this list of conditions and the following disclaimer.
0016  * 2. Redistributions in binary form must reproduce the above copyright
0017  *    notice, this list of conditions and the following disclaimer in the
0018  *    documentation and/or other materials provided with the distribution.
0019  *
0020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0021  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0022  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0023  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0024  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0025  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0026  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0027  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0028  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0029  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0030  * POSSIBILITY OF SUCH DAMAGE.
0031  */
0032
0033 #include <rtems/score/cpu.h>
0034
0035 #include <bsp/start.h>
0036 #include <rtems/score/assert.h>
0037
0038 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
0039 {
0040   volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
0041
0042   _Assert(cpu_index == 1);
0043
0044   /*
0045    * Enable the second CPU.
0046    */
0047   _ARM_Data_synchronization_barrier();
0048   _ARM_Instruction_synchronization_barrier();
0049   *kick_address = (uint32_t) _start;
0050   _ARM_Data_synchronization_barrier();
0051   _ARM_Instruction_synchronization_barrier();
0052   _ARM_Send_event();
0053
0054   return true;
0055 }