xilinx-zynqmp/include/bsp.h

0001 /**
0002  * @file
0003  * @ingroup RTEMSBSPsARMZynqMP
0004  * @brief Global BSP definitions.
0005  */
0006
0007 /*
0008  * SPDX-License-Identifier: BSD-2-Clause
0009  *
0010  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0011  *
0012  * Copyright (C) 2019 DornerWorks
0013  *
0014  * Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
0015  *        and Josh Whitehead <josh.whitehead@dornerworks.com>
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions
0019  * are met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0027  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0028  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0029  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0030  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0031  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0032  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0033  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0034  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0035  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0036  * POSSIBILITY OF SUCH DAMAGE.
0037  */
0038
0039 #ifndef LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
0040 #define LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
0041
0042 /**
0043  * @defgroup RTEMSBSPsARMZynqMP Xilinx Zynq UltraScale+ MPSoC
0044  *
0045  * @ingroup RTEMSBSPsARM
0046  *
0047  * @brief Xilinx Zynq UltraScale+ MPSoC Board Support Package.
0048  *
0049  * @{
0050  */
0051
0052 #include <bspopts.h>
0053
0054 #define BSP_FEATURE_IRQ_EXTENSION
0055
0056 #ifndef ASM
0057
0058 #include <rtems.h>
0059
0060 #include <bsp/default-initial-extension.h>
0061 #include <bsp/start.h>
0062
0063 #include <dev/serial/zynq-uart-zynqmp.h>
0064
0065 #ifdef __cplusplus
0066 extern "C" {
0067 #endif /* __cplusplus */
0068
0069 #define BSP_ARM_GIC_CPUIF_BASE 0xf9020000
0070
0071 #define BSP_ARM_GIC_DIST_BASE 0xf9010000
0072
0073 #define BSP_ARM_A9MPCORE_SCU_BASE 0
0074
0075 #define BSP_ARM_A9MPCORE_GT_BASE 0
0076
0077 /**
0078  * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
0079  *
0080  * Provide in the application to override the defaults in the BSP.
0081  */
0082 BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
0083
0084 void zynqmp_debug_console_flush(void);
0085
0086 #ifdef __cplusplus
0087 }
0088 #endif /* __cplusplus */
0089
0090 #endif /* ASM */
0091
0092 /** @} */
0093
0094 #endif /* LIBBSP_ARM_XILINX_ZYNQMP_BSP_H */