include/bsp/memory.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMZynqMPRPU
0005  *
0006  * @brief This header file provides BSP-specific memory interfaces.
0007  */
0008
0009 /*
0010  * Copyright (C) 2024 embedded brains GmbH & Co. KG
0011  * Copyright (C) 2023 Reflex Aerospace GmbH
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H
0036 #define LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H
0037
0038 #include <rtems/score/armv7-pmsa.h>
0039
0040 #ifdef __cplusplus
0041 extern "C" {
0042 #endif /* __cplusplus */
0043
0044 /**
0045  * @addtogroup RTEMSBSPsARMZynqMPRPU
0046  *
0047  * @{
0048  */
0049
0050 extern char zynqmp_memory_atcm_begin[];
0051 extern char zynqmp_memory_atcm_end[];
0052 extern char zynqmp_memory_atcm_size[];
0053
0054 extern char zynqmp_memory_btcm_begin[];
0055 extern char zynqmp_memory_btcm_end[];
0056 extern char zynqmp_memory_btcm_size[];
0057
0058 extern char zynqmp_memory_ddr_begin[];
0059 extern char zynqmp_memory_ddr_end[];
0060 extern char zynqmp_memory_ddr_size[];
0061
0062 extern char zynqmp_memory_nocache_begin[];
0063 extern char zynqmp_memory_nocache_end[];
0064 extern char zynqmp_memory_nocache_size[];
0065
0066 extern char zynqmp_memory_devpl_begin[];
0067 extern char zynqmp_memory_devpl_end[];
0068 extern char zynqmp_memory_devpl_size[];
0069
0070 extern char zynqmp_memory_devps_begin[];
0071 extern char zynqmp_memory_devps_end[];
0072 extern char zynqmp_memory_devps_size[];
0073
0074 extern char zynqmp_memory_ocm_begin[];
0075 extern char zynqmp_memory_ocm_end[];
0076 extern char zynqmp_memory_ocm_size[];
0077
0078 /**
0079  * @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
0080  *
0081  * Provide in the application to override the defaults in the BSP.
0082  */
0083 void zynqmp_setup_mpu_and_cache(void);
0084
0085 /**
0086  * @brief This table defines the Zynq UltraScale+ MPSoC or RFSoC specific MPU
0087  * regions.
0088  *
0089  * The table entry count is provided by ::zynqmp_mpu_region_count.
0090  *
0091  * The application may provide this table to override the defaults in the BSP.
0092  */
0093 extern const ARMV7_PMSA_Region zynqmp_mpu_regions[];
0094
0095 /**
0096  * @brief This constant contains the entry count of the ::zynqmp_mpu_regions
0097  *   table.
0098  */
0099 extern const size_t zynqmp_mpu_region_count;
0100
0101 /** @} */
0102
0103 #ifdef __cplusplus
0104 }
0105 #endif /* __cplusplus */
0106
0107 #endif /* LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_MEMORY_H */