xilinx-zynqmp-rpu/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMZynqMPRPU
0005  *
0006  * @brief This header file provides BSP-specific interfaces.
0007  */
0008
0009 /*
0010  * Copyright (C) 2024 embedded brains GmbH & Co. KG
0011  * Copyright (C) 2023 Reflex Aerospace GmbH
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
0036 #define LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
0037
0038 /**
0039  * @defgroup RTEMSBSPsARMZynqMPRPU \
0040  *   AMD Zynq UltraScale+ MPSoC and RFSoC - Real-time Processing Unit
0041  *
0042  * @ingroup RTEMSBSPsARM
0043  *
0044  * @brief This group contains the BSP for the Real-time Processing Unit (RPU)
0045  *   contained in AMD Zynq UltraScale+ MPSoC and RFSoC devices.
0046  *
0047  * @{
0048  */
0049
0050 #include <bspopts.h>
0051
0052 #define BSP_FEATURE_IRQ_EXTENSION
0053
0054 #ifndef ASM
0055
0056 #include <rtems.h>
0057
0058 #include <bsp/default-initial-extension.h>
0059
0060 #include <dev/serial/zynq-uart-zynqmp.h>
0061
0062 #ifdef __cplusplus
0063 extern "C" {
0064 #endif /* __cplusplus */
0065
0066
0067 #define BSP_ARM_GIC_CPUIF_BASE 0x00F9001000
0068
0069 #define BSP_ARM_GIC_DIST_BASE 0xF9000000
0070
0071 #if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_CORE_INDEX != 0
0072 #define BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY
0073 #endif
0074
0075 void zynqmp_debug_console_flush(void);
0076
0077 #ifdef __cplusplus
0078 }
0079 #endif /* __cplusplus */
0080
0081 #endif /* ASM */
0082
0083 /** @} */
0084
0085 #endif /* LIBBSP_ARM_XILINX_ZYNQMP_BSP_H */