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File indexing completed on 2025-05-11 08:23:39
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * @ingroup zynq_slcr 0006 * @brief SLCR support. 0007 */ 0008 0009 /* 0010 * 0011 * Copyright (c) 2017 0012 * NSF Center for High-Performance Reconfigurable Computing (CHREC), 0013 * University of Pittsburgh. All rights reserved. 0014 * 0015 * Redistribution and use in source and binary forms, with or without 0016 * modification, are permitted provided that the following conditions are 0017 * met: 0018 * 1. Redistributions of source code must retain the above copyright 0019 * notice, this list of conditions and the following disclaimer. 0020 * 2. Redistributions in binary form must reproduce the above copyright 0021 * notice, this list of conditions and the following disclaimer in the 0022 * documentation and/or other materials provided with the distribution. 0023 * 0024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 0025 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 0026 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 0027 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER 0028 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 0029 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 0030 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 0031 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 0032 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 0033 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 0034 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0035 * 0036 * The views and conclusions contained in the software and documentation 0037 * are those of the authors and should not be interpreted as representing 0038 * official policies, either expressed or implied, of CHREC. 0039 * 0040 * Author: Patrick Gauvin <gauvin@hcs.ufl.edu> 0041 */ 0042 0043 /** 0044 * @defgroup zynq_slcr SLCR Support 0045 * @ingroup arm_zynq 0046 * @brief SLCR Support 0047 */ 0048 0049 #ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_H 0050 #define LIBBSP_ARM_XILINX_ZYNQ_SLCR_H 0051 0052 #include <stdint.h> 0053 0054 #ifdef __cplusplus 0055 extern "C" { 0056 #endif /* __cplusplus */ 0057 0058 /** 0059 * @brief Set the mask that allows the FPGA resets to be modified. 0060 * 0061 * Bit 0 corresponds to FPGA0_OUT_RST, and bit 3 to FPGA3_OUT_RST. Setting a 0062 * bit in the mask to 1 allows calls to zynq_slcr_fpga_clk_rst to modify that 0063 * reset. The default mask is 0xf. 0064 */ 0065 void zynq_slcr_fpga_clk_rst_mask_set( 0066 uint32_t mask 0067 ); 0068 0069 /** 0070 * @brief Control the FPGA reset values. 0071 * 0072 * @param val Bits 0 through 3 correspond to FPGA RST 0 through 3. A bit value 0073 * of 1 asserts the reset. 0074 */ 0075 void zynq_slcr_fpga_clk_rst( 0076 uint32_t val 0077 ); 0078 0079 /** 0080 * @brief Control the level shifters between the PS and PL. 0081 * 0082 * @param val Acceptable values are ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE, 0083 * ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL, and ZYNQ_SLCR_LVL_SHFTR_EN_ALL. 0084 */ 0085 void zynq_slcr_level_shifter_enable( 0086 uint32_t val 0087 ); 0088 0089 #ifdef __cplusplus 0090 } 0091 #endif /* __cplusplus */ 0092 0093 #endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_H */
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