dev/slcr/zynq-slcr-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup zynq_slcr
0006  * @brief SLCR register definitions.
0007  */
0008
0009 /*
0010  * Copyright (c) 2017
0011  *  NSF Center for High-Performance Reconfigurable Computing (CHREC),
0012  *  University of Pittsburgh.  All rights reserved.
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions are
0016  * met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0024  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0025  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0026  * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
0027  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0029  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0030  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0031  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0032  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0033  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0034  *
0035  * The views and conclusions contained in the software and documentation
0036  * are those of the authors and should not be interpreted as representing
0037  * official policies, either expressed or implied, of CHREC.
0038  *
0039  * Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
0040  */
0041
0042 /**
0043  * @defgroup zynq_slcr_regs SLCR Register Definitions
0044  * @ingroup zynq_slcr
0045  * @brief SLCR Register Definitions
0046  */
0047
0048 #ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
0049 #define LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
0050
0051 #include <bsp/utility.h>
0052
0053 #ifdef __cplusplus
0054 extern "C" {
0055 #endif /* __cplusplus */
0056
0057 #define ZYNQ_SLCR_BASE_ADDR ( 0xF8000000 )
0058
0059 #define ZYNQ_SLCR_LOCK_OFF ( 0x4 )
0060 #define ZYNQ_SLCR_UNLOCK_OFF ( 0x8 )
0061 #define ZYNQ_SLCR_FPGA_RST_CTRL_OFF ( 0x240 )
0062 #define ZYNQ_SLCR_PSS_IDCODE_OFF ( 0x530 )
0063 #define ZYNQ_SLCR_LVL_SHFTR_EN_OFF ( 0x900 )
0064
0065 #define ZYNQ_SLCR_LOCK_KEY ( 0x767b )
0066 #define ZYNQ_SLCR_UNLOCK_KEY ( 0xdf0d )
0067
0068 /** \brief Get FPGA0_OUT_RST (bit 0) through FPGA3_OUT_RST fields (bit 3). */
0069 #define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET( reg ) \
0070   BSP_FLD32GET( reg, 0, 3 )
0071 #define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST( val ) BSP_FLD32( val, 0, 3 )
0072
0073 /* NOTE: QEMU gives a value of 0 for the pss_idcode. */
0074 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_GET( reg ) BSP_FLD32GET( reg, 12, 16 )
0075 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z007s ( 0x03 )
0076 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z012s ( 0x1c )
0077 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z014s ( 0x08 )
0078 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z010 ( 0x02 )
0079 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z015 ( 0x1b )
0080 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z020 ( 0x07 )
0081 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z030 ( 0x0c )
0082 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z035 ( 0x12 )
0083 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z045 ( 0x11 )
0084 #define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z100 ( 0x16 )
0085
0086 #define ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE ( 0 )
0087 #define ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL ( 0xA )
0088 #define ZYNQ_SLCR_LVL_SHFTR_EN_ALL ( 0xF )
0089
0090 static inline void zynq_slcr_write32(
0091   const uint32_t reg_off,
0092   const uint32_t val
0093 )
0094 {
0095   volatile uint32_t *slcr_reg;
0096   slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off );
0097   *slcr_reg = val;
0098 }
0099
0100 static inline uint32_t zynq_slcr_read32(
0101   const uint32_t reg_off
0102 )
0103 {
0104   volatile uint32_t *slcr_reg;
0105   slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off);
0106   return *slcr_reg;
0107 }
0108
0109 #ifdef __cplusplus
0110 }
0111 #endif /* __cplusplus */
0112
0113 #endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H */