dev/devcfg/zynq-devcfg-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup zynq_devcfg
0006  * @brief Device configuration interface register definitions.
0007  */
0008
0009 /*
0010  * Copyright (c) 2016
0011  *  NSF Center for High-Performance Reconfigurable Computing (CHREC),
0012  *  University of Florida.  All rights reserved.
0013  * Copyright (c) 2017
0014  *  NSF Center for High-Performance Reconfigurable Computing (CHREC),
0015  *  University of Pittsburgh.  All rights reserved.
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions are
0019  * met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0027  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0028  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0029  * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
0030  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0031  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0032  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0033  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0034  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0035  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0036  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0037  *
0038  * The views and conclusions contained in the software and documentation
0039  * are those of the authors and should not be interpreted as representing
0040  * official policies, either expressed or implied, of CHREC.
0041  *
0042  * Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
0043  */
0044
0045 /**
0046  * @defgroup zynq_devcfg_regs Device Configuration Interface Register Definitions
0047  * @ingroup zynq_devcfg
0048  * @brief Device Configuration Interface Register Definitions
0049  */
0050
0051 #ifndef LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
0052 #define LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
0053
0054 #include <stdint.h>
0055 #include <bsp/utility.h>
0056
0057 #ifdef __cplusplus
0058 extern "C" {
0059 #endif /* __cplusplus */
0060
0061 /* Zynq-7000 series devcfg address */
0062 #define ZYNQ_DEVCFG_BASE_ADDR 0xF8007000UL
0063 /* For use with the PCAP DMA */
0064 #define ZYNQ_DEVCFG_BITSTREAM_ADDR 0xFFFFFFFFUL
0065 #define ZYNQ_DEVCFG_INTERRUPT_VECTOR 40
0066
0067 typedef struct {
0068   uint32_t ctrl;
0069 #define ZYNQ_DEVCFG_CTRL_FORCE_RST( val ) BSP_FLD32( val, 31, 31 )
0070 #define ZYNQ_DEVCFG_CTRL_FORCE_RST_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
0071 #define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET( reg ) BSP_FLD32GET( reg, 30, 30 )
0072 #define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B( val ) BSP_FLD32( val, 30, 30 )
0073 #define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET( reg ) BSP_FLD32GET( reg, 29, 29 )
0074 #define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K( val ) BSP_FLD32( val, 29, 29 )
0075 #define ZYNQ_DEVCFG_CTRL_PCAP_PR( val ) BSP_FLD32( val, 27, 27 )
0076 #define ZYNQ_DEVCFG_CTRL_PCAP_PR_GET( reg ) BSP_FLD32GET( reg, 27, 27 )
0077 #define ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP ( 0 )
0078 #define ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP ( 1 )
0079 #define ZYNQ_DEVCFG_CTRL_PCAP_MODE( val ) BSP_FLD32( val, 26, 26 )
0080 #define ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET( reg ) BSP_FLD32GET( reg, 26, 26 )
0081 #define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN( val ) BSP_FLD32( val, 25, 25 )
0082 #define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET( reg ) \
0083   BSP_FLD32GET( reg, 25, 25 )
0084 #define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN( val ) BSP_FLD32( val, 24, 24 )
0085 #define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET( reg ) BSP_FLD32GET( reg, 24, 24 )
0086 #define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS( val ) BSP_FLD32( val, 23, 23 )
0087 #define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET( reg ) BSP_FLD32GET( reg, 23, 23 )
0088 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE( val ) BSP_FLD32( val, 12, 12 )
0089 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
0090 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM ( 0 )
0091 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE ( 1 )
0092 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN( val ) BSP_FLD32( val, 9, 11 )
0093 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET( reg ) BSP_FLD32GET( reg, 9, 11 )
0094 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE ( 0x3 )
0095 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE ( 0x0 )
0096 #define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN ( 0x1 )
0097 #define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN( val ) BSP_FLD32( val, 8, 8 )
0098 #define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
0099 #define ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET( reg ) BSP_FLD32GET( reg, 7, 7 )
0100 #define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN( val ) BSP_FLD32( val, 6, 6 )
0101 #define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET( reg ) BSP_FLD32GET( reg, 6, 6 )
0102 #define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN( val ) BSP_FLD32( val, 5, 5 )
0103 #define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET( reg ) BSP_FLD32GET( reg, 5, 5 )
0104 #define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN( val ) BSP_FLD32( val, 4, 4 )
0105 #define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
0106 #define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN( val ) BSP_FLD32( val, 3, 3 )
0107 #define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET( reg ) BSP_FLD32GET( reg, 3, 3 )
0108 #define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN( val ) BSP_FLD32( val, 0, 2 )
0109 #define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET( reg ) BSP_FLD32GET( reg, 0, 2 )
0110 #define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE ( 0x3 )
0111 #define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS ( 0x0 )
0112 #define ZYNQ_DEVCFG_CTRL_RESERVED_BITS ( 0x6000 )
0113   uint32_t lock;
0114   uint32_t cfg;
0115   /* int_sts and int_mask directly overlap, so they share the ZYNQ_DEVCFG_INT_*
0116    * macros */
0117   uint32_t int_sts;
0118   uint32_t int_mask;
0119 #define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT BSP_BIT32( 27 )
0120 #define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET( reg ) \
0121   BSP_FLD32GET( reg, 27, 27 )
0122 #define ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET( reg ) BSP_FLD32GET( reg, 22, 22 )
0123 #define ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET( reg ) BSP_FLD32GET( reg, 21, 21 )
0124 #define ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET( reg ) BSP_FLD32GET( reg, 20, 20 )
0125 #define ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET( reg ) \
0126   BSP_FLD32GET( reg, 18, 18 )
0127 #define ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET( reg ) \
0128   BSP_FLD32GET( reg, 15, 15 )
0129 #define ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET( reg ) BSP_FLD32GET( reg, 14, 14 )
0130 #define ZYNQ_DEVCFG_INT_DMA_DONE_INT BSP_BIT32( 13 )
0131 #define ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 13, 13 )
0132 #define ZYNQ_DEVCFG_INT_D_P_DONE_INT BSP_BIT32( 12 )
0133 #define ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
0134 #define ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET( reg ) \
0135   BSP_FLD32GET( reg, 11, 11 )
0136 #define ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET( reg ) \
0137   BSP_FLD32GET( reg, 6, 6 )
0138 #define ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET( reg ) \
0139   BSP_FLD32GET( reg, 5, 5 )
0140 #define ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
0141 #define ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET( reg ) \
0142   BSP_FLD32GET( reg, 3, 3 )
0143 #define ZYNQ_DEVCFG_INT_PCFG_DONE_INT BSP_BIT32( 2 )
0144 #define ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 2, 2 )
0145 #define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT BSP_BIT32( 1 )
0146 #define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET( reg ) \
0147   BSP_FLD32GET( reg, 1, 1 )
0148 #define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT BSP_BIT32( 0 )
0149 #define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET( reg ) \
0150   BSP_FLD32GET( reg, 0, 0 )
0151 #define ZYNQ_DEVCFG_INT_ALL ( 0xf8f7f87f )
0152   uint32_t status;
0153 #define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F( val ) BSP_FLD32( val, 31, 31 )
0154 #define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
0155 #define ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
0156   uint32_t dma_src_addr;
0157 #define ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
0158   uint32_t dma_dst_addr;
0159 #define ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
0160   uint32_t dma_src_len;
0161 #define ZYNQ_DEVCFG_DMA_SRC_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
0162   uint32_t dma_dest_len; /* (sic) */
0163 #define ZYNQ_DEVCFG_DMA_DEST_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
0164   uint32_t reserved0;
0165   uint32_t multiboot_addr;
0166   uint32_t reserved1;
0167   uint32_t unlock;
0168   uint32_t reserved2[18];
0169   uint32_t mctrl;
0170 #define ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET( reg ) BSP_FLD32GET( reg, 28, 31 )
0171 #define ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0 0x0
0172 #define ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0 0x1
0173 #define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0 0x2
0174 #define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1 0x3
0175 #define ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
0176 #define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
0177 #define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK( val ) BSP_FLD32( val, 4, 4 )
0178 #define ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS ( 0x800000 )
0179 #define ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ( 0x3 )
0180 #define ZYNQ_DEVCFG_MCTRL_SET( reg, val ) ( ( ( reg ) & \
0181   ~ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ) | \
0182   ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS | ( val ) )
0183   uint32_t reserved3[32];
0184   uint32_t xadcif_cfg;
0185   uint32_t xadcif_int_sts;
0186   uint32_t xadcif_int_mask;
0187   uint32_t xadcif_msts;
0188   uint32_t xadcif_cmdfifo;
0189   uint32_t xadcif_rdfifo;
0190   uint32_t xadcif_mctrl;
0191 } zynq_devcfg_regs;
0192
0193 #ifdef __cplusplus
0194 }
0195 #endif /* __cplusplus */
0196
0197 #endif /* LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H */