include/bsp/irq.h

0001 /**
0002  * @file
0003  * @ingroup zynq_interrupt
0004  * @brief Interrupt definitions.
0005  */
0006
0007 /*
0008  * SPDX-License-Identifier: BSD-2-Clause
0009  *
0010  * Copyright (C) 2013 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
0035 #define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
0036
0037 #ifndef ASM
0038
0039 #include <rtems/irq-extension.h>
0040
0041 #include <bsp/arm-a9mpcore-irq.h>
0042 #include <dev/irq/arm-gic-irq.h>
0043
0044 #ifdef __cplusplus
0045 extern "C" {
0046 #endif /* __cplusplus */
0047
0048 /**
0049  * @defgroup zynq_interrupt Interrupt Support
0050  * @ingroup RTEMSBSPsARMZynq
0051  * @brief Interrupt Support
0052  * @{
0053  */
0054
0055 #define ZYNQ_IRQ_CPU_0 32
0056 #define ZYNQ_IRQ_CPU_1 33
0057 #define ZYNQ_IRQ_L2_CACHE 34
0058 #define ZYNQ_IRQ_OCM 35
0059 #define ZYNQ_IRQ_PMU_0 37
0060 #define ZYNQ_IRQ_PMU_1 38
0061 #define ZYNQ_IRQ_XADC 39
0062 #define ZYNQ_IRQ_DVI 40
0063 #define ZYNQ_IRQ_SWDT 41
0064 #define ZYNQ_IRQ_TTC_0_0 42
0065 #define ZYNQ_IRQ_TTC_1_0 43
0066 #define ZYNQ_IRQ_TTC_2_0 44
0067 #define ZYNQ_IRQ_DMAC_ABORT 45
0068 #define ZYNQ_IRQ_DMAC_0 46
0069 #define ZYNQ_IRQ_DMAC_1 47
0070 #define ZYNQ_IRQ_DMAC_2 48
0071 #define ZYNQ_IRQ_DMAC_3 49
0072 #define ZYNQ_IRQ_SMC 50
0073 #define ZYNQ_IRQ_QUAD_SPI 51
0074 #define ZYNQ_IRQ_GPIO 52
0075 #define ZYNQ_IRQ_USB_0 53
0076 #define ZYNQ_IRQ_ETHERNET_0 54
0077 #define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
0078 #define ZYNQ_IRQ_SDIO_0 56
0079 #define ZYNQ_IRQ_I2C_0 57
0080 #define ZYNQ_IRQ_SPI_0 58
0081 #define ZYNQ_IRQ_UART_0 59
0082 #define ZYNQ_IRQ_CAN_0 60
0083 #define ZYNQ_IRQ_FPGA_0 61
0084 #define ZYNQ_IRQ_FPGA_1 62
0085 #define ZYNQ_IRQ_FPGA_2 63
0086 #define ZYNQ_IRQ_FPGA_3 64
0087 #define ZYNQ_IRQ_FPGA_4 65
0088 #define ZYNQ_IRQ_FPGA_5 66
0089 #define ZYNQ_IRQ_FPGA_6 67
0090 #define ZYNQ_IRQ_FPGA_7 68
0091 #define ZYNQ_IRQ_TTC_0_1 69
0092 #define ZYNQ_IRQ_TTC_1_1 70
0093 #define ZYNQ_IRQ_TTC_2_1 71
0094 #define ZYNQ_IRQ_DMAC_4 72
0095 #define ZYNQ_IRQ_DMAC_5 73
0096 #define ZYNQ_IRQ_DMAC_6 74
0097 #define ZYNQ_IRQ_DMAC_7 75
0098 #define ZYNQ_IRQ_USB_1 76
0099 #define ZYNQ_IRQ_ETHERNET_1 77
0100 #define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
0101 #define ZYNQ_IRQ_SDIO_1 79
0102 #define ZYNQ_IRQ_I2C_1 80
0103 #define ZYNQ_IRQ_SPI_1 81
0104 #define ZYNQ_IRQ_UART_1 82
0105 #define ZYNQ_IRQ_CAN_1 83
0106 #define ZYNQ_IRQ_FPGA_8 84
0107 #define ZYNQ_IRQ_FPGA_9 85
0108 #define ZYNQ_IRQ_FPGA_10 86
0109 #define ZYNQ_IRQ_FPGA_11 87
0110 #define ZYNQ_IRQ_FPGA_12 88
0111 #define ZYNQ_IRQ_FPGA_13 89
0112 #define ZYNQ_IRQ_FPGA_14 90
0113 #define ZYNQ_IRQ_FPGA_15 91
0114 #define ZYNQ_IRQ_PARITY 92
0115
0116 #define BSP_INTERRUPT_VECTOR_COUNT 93
0117
0118 /** @} */
0119
0120 #ifdef __cplusplus
0121 }
0122 #endif /* __cplusplus */
0123
0124 #endif /* ASM */
0125
0126 #endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */