xilinx-zynq/include/bsp.h

0001 /**
0002  * @file
0003  * @ingroup RTEMSBSPsARMZynq
0004  * @brief Global BSP definitions.
0005  */
0006
0007 /*
0008  * SPDX-License-Identifier: BSD-2-Clause
0009  *
0010  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H
0035 #define LIBBSP_ARM_XILINX_ZYNQ_BSP_H
0036
0037 /**
0038  * @defgroup RTEMSBSPsARMZynq Xilinx Zynq
0039  *
0040  * @ingroup RTEMSBSPsARM
0041  *
0042  * @brief Xilinx Zynq Board Support Package.
0043  *
0044  * @{
0045  */
0046
0047 #include <bspopts.h>
0048
0049 #define BSP_FEATURE_IRQ_EXTENSION
0050
0051 #ifndef ASM
0052
0053 #include <rtems.h>
0054
0055 #include <bsp/default-initial-extension.h>
0056 #include <bsp/start.h>
0057 #include <dev/serial/zynq-uart-zynq.h>
0058
0059 #ifdef __cplusplus
0060 extern "C" {
0061 #endif /* __cplusplus */
0062
0063 #define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000
0064
0065 #define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
0066
0067 #define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200
0068
0069 #define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
0070
0071 #define BSP_ARM_GIC_DIST_BASE 0xf8f01000
0072
0073 #define BSP_ARM_L2C_310_BASE 0xf8f02000
0074
0075 #define BSP_ARM_L2C_310_ID 0x410000c8
0076
0077 /**
0078  * @brief Zynq specific set up of the MMU.
0079  *
0080  * Provide in the application to override
0081  * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
0082  * AXI ports. You should add the specific regions that map into your
0083  * PL rather than just open the whole of the GP[01] address space up.
0084  */
0085 BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
0086
0087 uint32_t zynq_clock_cpu_1x(void);
0088
0089 #ifdef __cplusplus
0090 }
0091 #endif /* __cplusplus */
0092
0093 #endif /* ASM */
0094
0095 /** @} */
0096
0097 #endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */