dev/slcr/zynq-slcr.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * SLCR Support Implementation
0005  *
0006  * At this point, only a few operations related to programming the FPGA are
0007  * supported.
0008  *
0009  * Copyright (c) 2017
0010  *  NSF Center for High-Performance Reconfigurable Computing (CHREC),
0011  *  University of Pittsburgh.  All rights reserved.
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions are
0015  * met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
0023  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
0024  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
0025  * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
0026  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0027  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
0028  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
0029  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
0030  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
0031  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033  *
0034  * The views and conclusions contained in the software and documentation
0035  * are those of the authors and should not be interpreted as representing
0036  * official policies, either expressed or implied, of CHREC.
0037  *
0038  * Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
0039  */
0040 #include <stdint.h>
0041 #include <rtems.h>
0042 #include <dev/slcr/zynq-slcr.h>
0043 #include <dev/slcr/zynq-slcr-regs.h>
0044
0045 static uint32_t rst_mask = 0xf;
0046
0047 #if RTEMS_INTERRUPT_LOCK_NEEDS_OBJECT
0048 static rtems_interrupt_lock zynq_slcr_lock =
0049     RTEMS_INTERRUPT_LOCK_INITIALIZER( "zynq_slcr" );
0050 #endif
0051
0052 static inline void slcr_unlock( void )
0053 {
0054   zynq_slcr_write32( ZYNQ_SLCR_UNLOCK_OFF, ZYNQ_SLCR_UNLOCK_KEY );
0055 }
0056
0057 static inline void slcr_lock( void )
0058 {
0059   zynq_slcr_write32( ZYNQ_SLCR_LOCK_OFF, ZYNQ_SLCR_LOCK_KEY );
0060 }
0061
0062 void zynq_slcr_fpga_clk_rst_mask_set(
0063   uint32_t mask
0064 )
0065 {
0066   rtems_interrupt_lock_context lcontext;
0067
0068   rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
0069   rst_mask = 0xf & mask;
0070   rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
0071 }
0072
0073 void zynq_slcr_fpga_clk_rst(
0074   uint32_t val
0075 )
0076 {
0077   uint32_t rst_ctrl;
0078   rtems_interrupt_lock_context lcontext;
0079
0080   rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
0081   slcr_unlock();
0082   rst_ctrl = ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET(
0083     zynq_slcr_read32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF )
0084   );
0085   /* Only modify resets that are set in the mask */
0086   zynq_slcr_write32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF,
0087     ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST(
0088       ( ~rst_mask & rst_ctrl ) | ( rst_mask & val )
0089     )
0090   );
0091   slcr_lock();
0092   rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
0093 }
0094
0095 void zynq_slcr_level_shifter_enable(
0096   uint32_t val
0097 )
0098 {
0099   rtems_interrupt_lock_context lcontext;
0100
0101   rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
0102   slcr_unlock();
0103   zynq_slcr_write32( ZYNQ_SLCR_LVL_SHFTR_EN_OFF, val );
0104   slcr_lock();
0105   rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
0106 }