tms570/start/tms570_tcram_tests.c

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This source file contains TCRAM selftest functions.
0009  */
0010
0011 /*
0012  * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
0013  *
0014  * Czech Technical University in Prague
0015  * Zikova 1903/4
0016  * 166 36 Praha 6
0017  * Czech Republic
0018  *
0019  * Algorithms are based on Ti manuals and Ti HalCoGen generated
0020  * code available under following copyright.
0021  *
0022  * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
0023  *
0024  *
0025  *  Redistribution and use in source and binary forms, with or without
0026  *  modification, are permitted provided that the following conditions
0027  *  are met:
0028  *
0029  *    Redistributions of source code must retain the above copyright
0030  *    notice, this list of conditions and the following disclaimer.
0031  *
0032  *    Redistributions in binary form must reproduce the above copyright
0033  *    notice, this list of conditions and the following disclaimer in the
0034  *    documentation and/or other materials provided with the
0035  *    distribution.
0036  *
0037  *    Neither the name of Texas Instruments Incorporated nor the names of
0038  *    its contributors may be used to endorse or promote products derived
0039  *    from this software without specific prior written permission.
0040  *
0041  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0042  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0043  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0044  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0045  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0046  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0047  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0048  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0049  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0050  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0051  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0052  *
0053  */
0054
0055 #include <stdint.h>
0056 #include <bsp/tms570.h>
0057 #include <bsp/tms570_selftest.h>
0058 #include <bsp/tms570_hwinit.h>
0059
0060 #if TMS570_VARIANT == 3137
0061
0062 #define tcramA1bitError (*(volatile uint32_t *)(0x08400000U))
0063 #define tcramA2bitError (*(volatile uint32_t *)(0x08400010U))
0064
0065 #define tcramB1bitError (*(volatile uint32_t *)(0x08400008U))
0066 #define tcramB2bitError (*(volatile uint32_t *)(0x08400018U))
0067
0068 #define tcramA1bit      (*(volatile uint64_t *)(0x08000000U))
0069 #define tcramA2bit      (*(volatile uint64_t *)(0x08000010U))
0070
0071 #define tcramB1bit      (*(volatile uint64_t *)(0x08000008U))
0072 #define tcramB2bit      (*(volatile uint64_t *)(0x08000018U))
0073
0074 /**
0075  * @brief Check TCRAM ECC error detection logic (HCG:checkRAMECC)
0076  *
0077  * This function checks TCRAM ECC error detection and correction logic.
0078  * The function does not return in case of TCRAM error.
0079  * It calls bsp_selftest_fail_notification() instead.
0080  *
0081  */
0082 /* SourceId : SELFTEST_SourceId_034 */
0083 /* DesignId : SELFTEST_DesignId_019 */
0084 /* Requirements : HL_SR408 */
0085 void  tms570_check_tcram_ecc( void )
0086 {
0087   volatile uint64_t ramread;
0088   volatile uint32_t regread;
0089   uint32_t tcram1ErrStat, tcram2ErrStat = 0U;
0090
0091   uint64_t tcramA1_bk = tcramA1bit;
0092   uint64_t tcramB1_bk = tcramB1bit;
0093   uint64_t tcramA2_bk = tcramA2bit;
0094   uint64_t tcramB2_bk = tcramB2bit;
0095
0096   /* Clear RAMOCUUR before setting RAMTHRESHOLD register */
0097   TMS570_TCRAM1.RAMOCCUR = 0U;
0098   TMS570_TCRAM2.RAMOCCUR = 0U;
0099
0100   /* Set Single-bit Error Threshold Count as 1 */
0101   TMS570_TCRAM1.RAMTHRESHOLD = 1U;
0102   TMS570_TCRAM2.RAMTHRESHOLD = 1U;
0103
0104   /* Enable single bit error generation */
0105   TMS570_TCRAM1.RAMINTCTRL = 1U;
0106   TMS570_TCRAM2.RAMINTCTRL = 1U;
0107
0108   /* Enable writes to ECC RAM, enable ECC error response */
0109   TMS570_TCRAM1.RAMCTRL = 0x0005010AU;
0110   TMS570_TCRAM2.RAMCTRL = 0x0005010AU;
0111
0112   /* Force a single bit error in both the banks */
0113   _coreDisableRamEcc_();
0114   tcramA1bitError ^= 1U;
0115   tcramB1bitError ^= 1U;
0116   _coreEnableRamEcc_();
0117
0118   /* Read the corrupted data to generate single bit error */
0119   ramread = tcramA1bit;
0120   ramread = tcramB1bit;
0121   (void)ramread;
0122
0123   /* Check for error status */
0124   tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U;
0125   tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U;
0126   /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
0127   /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
0128   if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) {
0129         /* TCRAM module does not reflect 1-bit error reported by CPU */
0130     bsp_selftest_fail_notification(CHECKRAMECC_FAIL1);
0131   } else {
0132     if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) {
0133       /* TCRAM 1-bit error not flagged in ESM */
0134       bsp_selftest_fail_notification(CHECKRAMECC_FAIL2);
0135     } else {
0136       /* Clear single bit error flag in TCRAM module */
0137       TMS570_TCRAM1.RAMERRSTATUS = 0x1U;
0138       TMS570_TCRAM2.RAMERRSTATUS = 0x1U;
0139
0140       /* Clear ESM status */
0141       tms570_esm_channel_sr_clear(1, 26);
0142       tms570_esm_channel_sr_clear(1, 28);
0143     }
0144   }
0145
0146 #if 0
0147   /*
0148    * This test sequence requires that data abort exception
0149    * handler checks for ECC test write enable in RAMCTR (bit 8)
0150    * and if the access abort is intended then it should clear
0151    * error status TCRAM status register and checks and clears
0152    * ESM group3 uncorrectable TCRAM error channels.
0153    *
0154    * More modifications in BSP and RTEMS ARM support are
0155    * required to make this code work.
0156    */
0157
0158   /* Force a double bit error in both the banks */
0159   _coreDisableRamEcc_();
0160   tcramA2bitError ^= 3U;
0161   tcramB2bitError ^= 3U;
0162   _coreEnableRamEcc_();
0163
0164   /* Read the corrupted data to generate double bit error */
0165   ramread = tcramA2bit;
0166   ramread = tcramB2bit;
0167   /* read from location with 2-bit ECC error this will cause a data abort to be generated */
0168   /* See HalCoGen support src/sys/asm/dabort.asm */
0169   /* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */
0170 #endif
0171
0172   regread = TMS570_TCRAM1.RAMUERRADDR;
0173   regread = TMS570_TCRAM2.RAMUERRADDR;
0174   (void)regread;
0175
0176   /* disable writes to ECC RAM */
0177   TMS570_TCRAM1.RAMCTRL = 0x0005000AU;
0178   TMS570_TCRAM2.RAMCTRL = 0x0005000AU;
0179
0180   /* Compute correct ECC */
0181   tcramA1bit = tcramA1_bk;
0182   tcramB1bit = tcramB1_bk;
0183   tcramA2bit = tcramA2_bk;
0184   tcramB2bit = tcramB2_bk;
0185 }
0186
0187 #endif /* TMS570_VARIANT */