tms570/start/tms570_selftest_parity.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This source file contains parts of the parity based protection
0009  *   support.
0010  */
0011
0012 /*
0013  * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
0014  *
0015  * Czech Technical University in Prague
0016  * Zikova 1903/4
0017  * 166 36 Praha 6
0018  * Czech Republic
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #include <stdint.h>
0043 #include <stddef.h>
0044 #include <bsp/tms570.h>
0045 #include <rtems.h>
0046 #include <bsp/tms570_selftest.h>
0047 #include <bsp/tms570_selftest_parity.h>
0048
0049 /* HCG:het1ParityCheck */
0050 const tms570_selftest_par_desc_t
0051   tms570_selftest_par_het1_desc = {
0052   .esm_prim_grp  = 1,
0053   .esm_prim_chan = 7,
0054   .esm_sec_grp   = 0,
0055   .esm_sec_chan  = 0,
0056   .fail_code     = HET1PARITYCHECK_FAIL1,
0057   .ram_loc       = &NHET1RAMLOC,
0058   .par_loc       = &NHET1RAMPARLOC,
0059   .par_xor       = 0x00000001,
0060   .par_cr_reg    = &TMS570_NHET1.PCR,
0061   .par_cr_test   = TMS570_NHET_PCR_TEST,
0062   .par_st_reg    = NULL,
0063   .par_st_clear  = 0,
0064   .partest_fnc   = tms570_selftest_par_check_std,
0065   .fnc_data      = NULL
0066 };
0067
0068 /* HCG:htu1ParityCheck */
0069 const tms570_selftest_par_desc_t
0070   tms570_selftest_par_htu1_desc = {
0071   .esm_prim_grp  = 1,
0072   .esm_prim_chan = 8,
0073   .esm_sec_grp   = 0,
0074   .esm_sec_chan  = 0,
0075   .fail_code     = HTU1PARITYCHECK_FAIL1,
0076   .ram_loc       = &HTU1RAMLOC,
0077   .par_loc       = &HTU1PARLOC,
0078   .par_xor       = 0x00000001,
0079   .par_cr_reg    = &TMS570_HTU1.PCR,
0080   .par_cr_test   = TMS570_HTU_PCR_TEST,
0081   .par_st_reg    = &TMS570_HTU1.PAR,
0082   .par_st_clear  = TMS570_HTU_PAR_PEFT,
0083   .partest_fnc   = tms570_selftest_par_check_std,
0084   .fnc_data      = NULL
0085 };
0086
0087 /* HCG:het2ParityCheck */
0088 const tms570_selftest_par_desc_t
0089   tms570_selftest_par_het2_desc = {
0090   .esm_prim_grp  = 1,
0091   .esm_prim_chan = 7,
0092   .esm_sec_grp   = 1,
0093   .esm_sec_chan  = 34,
0094   .fail_code     = HET2PARITYCHECK_FAIL1,
0095   .ram_loc       = &NHET2RAMLOC,
0096   .par_loc       = &NHET2RAMPARLOC,
0097   .par_xor       = 0x00000001,
0098   .par_cr_reg    = &TMS570_NHET2.PCR,
0099   .par_cr_test   = TMS570_NHET_PCR_TEST,
0100   .par_st_reg    = NULL,
0101   .par_st_clear  = 0,
0102   .partest_fnc   = tms570_selftest_par_check_std,
0103   .fnc_data      = NULL
0104 };
0105
0106 /* HCG:htu2ParityCheck */
0107 const tms570_selftest_par_desc_t
0108   tms570_selftest_par_htu2_desc = {
0109   .esm_prim_grp  = 1,
0110   .esm_prim_chan = 8,
0111   .esm_sec_grp   = 0,
0112   .esm_sec_chan  = 0,
0113   .fail_code     = HTU2PARITYCHECK_FAIL1,
0114   .ram_loc       = &HTU2RAMLOC,
0115   .par_loc       = &HTU2PARLOC,
0116   .par_xor       = 0x00000001,
0117   .par_cr_reg    = &TMS570_HTU2.PCR,
0118   .par_cr_test   = TMS570_HTU_PCR_TEST,
0119   .par_st_reg    = &TMS570_HTU2.PAR,
0120   .par_st_clear  = TMS570_HTU_PAR_PEFT,
0121   .partest_fnc   = tms570_selftest_par_check_std,
0122   .fnc_data      = NULL
0123 };
0124
0125 /* HCG:adc1ParityCheck */
0126 const tms570_selftest_par_desc_t
0127   tms570_selftest_par_adc1_desc = {
0128   .esm_prim_grp  = 1,
0129   .esm_prim_chan = 19,
0130   .esm_sec_grp   = 0,
0131   .esm_sec_chan  = 0,
0132   .fail_code     = ADC1PARITYCHECK_FAIL1,
0133   .ram_loc       = &adcRAM1,
0134   .par_loc       = &adcPARRAM1,
0135   .par_xor       = 0xffffffff,
0136   .par_cr_reg    = &TMS570_ADC1.PARCR,
0137   .par_cr_test   = TMS570_ADC_PARCR_TEST,
0138   .par_st_reg    = NULL,
0139   .par_st_clear  = 0,
0140   .partest_fnc   = tms570_selftest_par_check_std,
0141   .fnc_data      = NULL
0142 };
0143
0144 /* HCG:adc2ParityCheck */
0145 const tms570_selftest_par_desc_t
0146   tms570_selftest_par_adc2_desc = {
0147   .esm_prim_grp  = 1,
0148   .esm_prim_chan = 1,
0149   .esm_sec_grp   = 0,
0150   .esm_sec_chan  = 0,
0151   .fail_code     = ADC2PARITYCHECK_FAIL1,
0152   .ram_loc       = &adcRAM2,
0153   .par_loc       = &adcPARRAM2,
0154   .par_xor       = 0xffffffff,
0155   .par_cr_reg    = &TMS570_ADC2.PARCR,
0156   .par_cr_test   = TMS570_ADC_PARCR_TEST,
0157   .par_st_reg    = NULL,
0158   .par_st_clear  = 0,
0159   .partest_fnc   = tms570_selftest_par_check_std,
0160   .fnc_data      = NULL
0161 };
0162
0163 /* HCG:can1ParityCheck */
0164 const tms570_selftest_par_desc_t
0165   tms570_selftest_par_can1_desc = {
0166   .esm_prim_grp  = 1,
0167   .esm_prim_chan = 21,
0168   .esm_sec_grp   = 0,
0169   .esm_sec_chan  = 0,
0170   .fail_code     = CAN1PARITYCHECK_FAIL1,
0171   .ram_loc       = &canRAM1,
0172   .par_loc       = &canPARRAM1,
0173   .par_xor       = 0x00001000,
0174   .par_cr_reg    = NULL,
0175   .par_cr_test   = 0,
0176   .par_st_reg    = NULL,
0177   .par_st_clear  = 0,
0178   .partest_fnc   = tms570_selftest_par_check_can,
0179   .fnc_data      = &TMS570_DCAN1
0180 };
0181
0182 /* HCG:can2ParityCheck */
0183 const tms570_selftest_par_desc_t
0184   tms570_selftest_par_can2_desc = {
0185   .esm_prim_grp  = 1,
0186   .esm_prim_chan = 23,
0187   .esm_sec_grp   = 0,
0188   .esm_sec_chan  = 0,
0189   .fail_code     = CAN2PARITYCHECK_FAIL1,
0190   .ram_loc       = &canRAM2,
0191   .par_loc       = &canPARRAM2,
0192   .par_xor       = 0x00001000,
0193   .par_cr_reg    = NULL,
0194   .par_cr_test   = 0,
0195   .par_st_reg    = NULL,
0196   .par_st_clear  = 0,
0197   .partest_fnc   = tms570_selftest_par_check_can,
0198   .fnc_data      = &TMS570_DCAN2
0199 };
0200
0201 /* HCG:can3ParityCheck */
0202 const tms570_selftest_par_desc_t
0203   tms570_selftest_par_can3_desc = {
0204   .esm_prim_grp  = 1,
0205   .esm_prim_chan = 22,
0206   .esm_sec_grp   = 0,
0207   .esm_sec_chan  = 0,
0208   .fail_code     = CAN3PARITYCHECK_FAIL1,
0209   .ram_loc       = &canRAM3,
0210   .par_loc       = &canPARRAM3,
0211   .par_xor       = 0x00001000,
0212   .par_cr_reg    = NULL,
0213   .par_cr_test   = 0,
0214   .par_st_reg    = NULL,
0215   .par_st_clear  = 0,
0216   .partest_fnc   = tms570_selftest_par_check_can,
0217   .fnc_data      = &TMS570_DCAN3
0218 };
0219
0220 /* HCG:vimParityCheck */
0221 const tms570_selftest_par_desc_t
0222   tms570_selftest_par_vim_desc = {
0223   .esm_prim_grp  = 1,
0224   .esm_prim_chan = 15,
0225   .esm_sec_grp   = 0,
0226   .esm_sec_chan  = 0,
0227   .fail_code     = VIMPARITYCHECK_FAIL1,
0228   .ram_loc       = &VIMRAMLOC,
0229   .par_loc       = &VIMRAMPARLOC,
0230   .par_xor       = 0x00000001,
0231   .par_cr_reg    = &TMS570_VIM.PARCTL,
0232   .par_cr_test   = TMS570_VIM_PARCTL_TEST,
0233   .par_st_reg    = &TMS570_VIM.PARFLG,
0234   .par_st_clear  = TMS570_VIM_PARFLG_PARFLG,
0235   .partest_fnc   = tms570_selftest_par_check_std,
0236   .fnc_data      = NULL
0237 };
0238
0239 /* HCG:dmaParityCheck */
0240 const tms570_selftest_par_desc_t
0241   tms570_selftest_par_dma_desc = {
0242   .esm_prim_grp  = 1,
0243   .esm_prim_chan = 3,
0244   .esm_sec_grp   = 0,
0245   .esm_sec_chan  = 0,
0246   .fail_code     = DMAPARITYCHECK_FAIL1,
0247   .ram_loc       = &DMARAMLOC,
0248   .par_loc       = &DMARAMPARLOC,
0249   .par_xor       = 0x00000001,
0250   .par_cr_reg    = &TMS570_DMA.DMAPCR,
0251   .par_cr_test   = TMS570_DMA_DMAPCR_TEST,
0252   .par_st_reg    = &TMS570_DMA.DMAPAR,
0253   .par_st_clear  = TMS570_DMA_DMAPAR_EDFLAG,
0254   .partest_fnc   = tms570_selftest_par_check_std,
0255   .fnc_data      = NULL
0256 };
0257
0258 /* HCG:mibspi1ParityCheck */
0259 const tms570_selftest_par_desc_t
0260   tms570_selftest_par_spi1_desc = {
0261   .esm_prim_grp  = 1,
0262   .esm_prim_chan = 17,
0263   .esm_sec_grp   = 0,
0264   .esm_sec_chan  = 0,
0265   .fail_code     = MIBSPI1PARITYCHECK_FAIL1,
0266   .ram_loc       = &MIBSPI1RAMLOC,
0267   .par_loc       = &mibspiPARRAM1,
0268   .par_xor       = 0x00000001,
0269   .par_cr_reg    = NULL,
0270   .par_cr_test   = 0,
0271   .par_st_reg    = NULL,
0272   .par_st_clear  = 0,
0273   .partest_fnc   = tms570_selftest_par_check_mibspi,
0274   .fnc_data      = &TMS570_SPI1
0275 };
0276
0277 /* HCG:mibspi3ParityCheck */
0278 const tms570_selftest_par_desc_t
0279   tms570_selftest_par_spi3_desc = {
0280   .esm_prim_grp  = 1,
0281   .esm_prim_chan = 18,
0282   .esm_sec_grp   = 0,
0283   .esm_sec_chan  = 0,
0284   .fail_code     = MIBSPI3PARITYCHECK_FAIL1,
0285   .ram_loc       = &MIBSPI3RAMLOC,
0286   .par_loc       = &mibspiPARRAM3,
0287   .par_xor       = 0x00000001,
0288   .par_cr_reg    = NULL,
0289   .par_cr_test   = 0,
0290   .par_st_reg    = NULL,
0291   .par_st_clear  = 0,
0292   .partest_fnc   = tms570_selftest_par_check_mibspi,
0293   .fnc_data      = &TMS570_SPI3
0294 };
0295
0296 /* HCG:mibspi5ParityCheck */
0297 const tms570_selftest_par_desc_t
0298   tms570_selftest_par_spi5_desc = {
0299   .esm_prim_grp  = 1,
0300   .esm_prim_chan = 24,
0301   .esm_sec_grp   = 0,
0302   .esm_sec_chan  = 0,
0303   .fail_code     = MIBSPI5PARITYCHECK_FAIL1,
0304   .ram_loc       = &MIBSPI5RAMLOC,
0305   .par_loc       = &mibspiPARRAM5,
0306   .par_xor       = 0x00000001,
0307   .par_cr_reg    = NULL,
0308   .par_cr_test   = 0,
0309   .par_st_reg    = NULL,
0310   .par_st_clear  = 0,
0311   .partest_fnc   = tms570_selftest_par_check_mibspi,
0312   .fnc_data      = &TMS570_SPI5
0313 };
0314
0315 /**
0316  * @brief run parity protection mechanism check for set of modules described by list.
0317  *
0318  * @param[in] desc_arr array of pointers to descriptors providing addresses
0319  *                     and ESM channels for individual peripherals.
0320  * @param[in] desc_cnt count of pointers in the array
0321  *
0322  * @return Void, in the case of error invokes bsp_selftest_fail_notification()
0323  */
0324 void tms570_selftest_par_run(
0325   const tms570_selftest_par_desc_t *
0326   const *desc_arr,
0327   int    desc_cnt
0328 )
0329 {
0330   int                              i;
0331   const tms570_selftest_par_desc_t *desc;
0332
0333   for ( i = 0; i < desc_cnt; i++ ) {
0334     desc = desc_arr[ i ];
0335     desc->partest_fnc( desc );
0336   }
0337 }