tms570/start/init_system.c

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This source file contains parts of the system initialization.
0009  */
0010
0011 /*
0012  * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc
0013  * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
0014  *
0015  *
0016  *  Redistribution and use in source and binary forms, with or without
0017  *  modification, are permitted provided that the following conditions
0018  *  are met:
0019  *
0020  *    Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  *
0023  *    Redistributions in binary form must reproduce the above copyright
0024  *    notice, this list of conditions and the following disclaimer in the
0025  *    documentation and/or other materials provided with the
0026  *    distribution.
0027  *
0028  *    Neither the name of Texas Instruments Incorporated nor the names of
0029  *    its contributors may be used to endorse or promote products derived
0030  *    from this software without specific prior written permission.
0031  *
0032  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0033  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0034  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0035  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0036  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0037  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0038  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0039  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0040  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0041  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0042  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0043  *
0044  */
0045
0046 #include <stdint.h>
0047 #include <stdbool.h>
0048 #include <bsp/tms570.h>
0049 #include <bsp/tms570-pinmux.h>
0050 #include <bsp/tms570_selftest.h>
0051 #include <bsp/tms570_hwinit.h>
0052
0053 /**
0054  * @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO)
0055  *
0056  */
0057 /* SourceId : SYSTEM_SourceId_002 */
0058 /* DesignId : SYSTEM_DesignId_002 */
0059 /* Requirements : HL_SR468 */
0060 void tms570_trim_lpo_init( void )
0061 {
0062   /** @b Initialize Lpo: */
0063   /** Load TRIM values from OTP if present else load user defined values */
0064   /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
0065   TMS570_SYS1.LPOMONCTL = TMS570_SYS1_LPOMONCTL_BIAS_ENABLE |
0066                           TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT * 0 |
0067                           TMS570_SYS1_LPOMONCTL_HFTRIM( 16 ) |
0068                           16; /* LFTRIM  */
0069 }
0070
0071 /* FIXME */
0072 enum tms570_flash_power_modes {
0073   TMS570_FLASH_SYS_SLEEP = 0U,     /**< Alias for flash bank power mode sleep   */
0074   TMS570_FLASH_SYS_STANDBY = 1U,   /**< Alias for flash bank power mode standby */
0075   TMS570_FLASH_SYS_ACTIVE = 3U     /**< Alias for flash bank power mode active  */
0076 };
0077
0078 /**
0079  * @brief Setup Flash memory parameters and timing (HCG:setupFlash)
0080  *
0081  */
0082 /* SourceId : SYSTEM_SourceId_003 */
0083 /* DesignId : SYSTEM_DesignId_003 */
0084 /* Requirements : HL_SR457 */
0085 void tms570_flash_init( void )
0086 {
0087   /** - Setup flash read mode, address wait states and data wait states */
0088   TMS570_FLASH.FRDCNTL = TMS570_FLASH_FRDCNTL_RWAIT( 3 ) |
0089                          TMS570_FLASH_FRDCNTL_ASWSTEN |
0090                          TMS570_FLASH_FRDCNTL_ENPIPE;
0091
0092   /** - Setup flash access wait states for bank 7 */
0093   TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0x5 );
0094   TMS570_FLASH.EEPROMCONFIG = TMS570_FLASH_EEPROMCONFIG_EWAIT( 3 ) |
0095                               TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN * 0 |
0096                               TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE( 2 );
0097
0098   /** - Disable write access to flash state machine registers */
0099   TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0xA );
0100
0101   /** - Setup flash bank power modes */
0102   TMS570_FLASH.FBFALLBACK = TMS570_FLASH_FBFALLBACK_BANKPWR7(
0103     TMS570_FLASH_SYS_ACTIVE ) |
0104                             TMS570_FLASH_FBFALLBACK_BANKPWR1(
0105     TMS570_FLASH_SYS_ACTIVE ) |
0106                             TMS570_FLASH_FBFALLBACK_BANKPWR0(
0107     TMS570_FLASH_SYS_ACTIVE );
0108 }
0109
0110 /**
0111  * @brief Power-up all peripherals and enable their clocks (HCG:periphInit)
0112  *
0113  */
0114 /* SourceId : SYSTEM_SourceId_004 */
0115 /* DesignId : SYSTEM_DesignId_004 */
0116 /* Requirements : HL_SR470 */
0117 void tms570_periph_init( void )
0118 {
0119   /** - Disable Peripherals before peripheral powerup*/
0120   TMS570_SYS1.CLKCNTL &= ~TMS570_SYS1_CLKCNTL_PENA;
0121
0122   /** - Release peripherals from reset and enable clocks to all peripherals */
0123   /** - Power-up all peripherals */
0124   TMS570_PCR1.PSPWRDWNCLR0 = 0xFFFFFFFFU;
0125   TMS570_PCR1.PSPWRDWNCLR1 = 0xFFFFFFFFU;
0126   TMS570_PCR1.PSPWRDWNCLR2 = 0xFFFFFFFFU;
0127   TMS570_PCR1.PSPWRDWNCLR3 = 0xFFFFFFFFU;
0128
0129 #if TMS570_VARIANT == 4357
0130   TMS570_PCR2.PSPWRDWNCLR0 = 0xFFFFFFFFU;
0131   TMS570_PCR2.PSPWRDWNCLR1 = 0xFFFFFFFFU;
0132   TMS570_PCR2.PSPWRDWNCLR2 = 0xFFFFFFFFU;
0133   TMS570_PCR2.PSPWRDWNCLR3 = 0xFFFFFFFFU;
0134
0135   TMS570_PCR3.PSPWRDWNCLR0 = 0xFFFFFFFFU;
0136   TMS570_PCR3.PSPWRDWNCLR1 = 0xFFFFFFFFU;
0137   TMS570_PCR3.PSPWRDWNCLR2 = 0xFFFFFFFFU;
0138   TMS570_PCR3.PSPWRDWNCLR3 = 0xFFFFFFFFU;
0139 #endif
0140
0141   /** - Enable Peripherals */
0142   TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA;
0143 }
0144
0145 /**
0146  * @brief TMS570 system hardware initialization (HCG:systemInit)
0147  *
0148  */
0149 /* SourceId : SYSTEM_SourceId_006 */
0150 /* DesignId : SYSTEM_DesignId_006 */
0151 /* Requirements : HL_SR471 */
0152 void tms570_system_hw_init( void )
0153 {
0154   uint32_t efc_check_status;
0155
0156   /* Configure PLL control registers and enable PLLs.
0157    * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
0158    * This initialization sequence performs all the tasks that are not
0159    * required to be done at full application speed while the PLL locks.
0160    */
0161   tms570_pll_init();
0162
0163   /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
0164    * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
0165    */
0166   efc_check_status = tms570_efc_check();
0167
0168   /* Enable clocks to peripherals and release peripheral reset */
0169   tms570_periph_init();
0170
0171   /* Configure device-level multiplexing and I/O multiplexing */
0172   tms570_pinmux_init();
0173
0174   /* Enable external memory interface */
0175   TMS570_SYS1.GPREG1 |= TMS570_SYS1_GPREG1_EMIF_FUNC;
0176
0177   if ( efc_check_status == 0U ) {
0178     /* Wait for eFuse controller self-test to complete and check results */
0179     if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
0180       bsp_selftest_fail_notification( EFCCHECK_FAIL1 );           /* device operation is not reliable */
0181     }
0182   } else if ( efc_check_status == 2U ) {
0183     /* Wait for eFuse controller self-test to complete and check results */
0184     if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
0185       bsp_selftest_fail_notification( EFCCHECK_FAIL1 );           /* device operation is not reliable */
0186     } else {
0187       bsp_selftest_fail_notification( EFCCHECK_FAIL2 );
0188     }
0189   } else {
0190     /* Empty */
0191   }
0192
0193   /** - Set up flash address and data wait states based on the target CPU clock frequency
0194    * The number of address and data wait states for the target CPU clock frequency are specified
0195    * in the specific part's datasheet.
0196    */
0197   tms570_flash_init();
0198
0199   /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
0200   tms570_trim_lpo_init();
0201
0202   /** - Wait for PLLs to start up and map clock domains to desired clock sources */
0203   tms570_map_clock_init();
0204 }
0205
0206 #if 0
0207 errata_PBIST_4
0208 vimInit
0209 #endif