tms570/start/init_esm.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This source file contains the error signaling module initialization.
0009  */
0010
0011 /*
0012  * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc
0013  * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
0014  *
0015  * Czech Technical University in Prague
0016  * Zikova 1903/4
0017  * 166 36 Praha 6
0018  * Czech Republic
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #include <stdint.h>
0043 #include <bsp/tms570.h>
0044 #include <bsp/tms570_hwinit.h>
0045
0046 /**
0047  * @brief Error signaling module initialization (HCG:esmInit)
0048  *
0049  */
0050 void tms570_esm_init( void )
0051 {
0052   /** - Disable error pin channels */
0053   TMS570_ESM.DEPAPR1 = 0xFFFFFFFFU;
0054   TMS570_ESM.IEPCR4 = 0xFFFFFFFFU;
0055
0056   /** - Disable interrupts */
0057   TMS570_ESM.IECR1 = 0xFFFFFFFFU;
0058   TMS570_ESM.IECR4 = 0xFFFFFFFFU;
0059
0060   /** - Clear error status flags */
0061   TMS570_ESM.SR[0U] = 0xFFFFFFFFU;
0062   TMS570_ESM.SR[1U] = 0xFFFFFFFFU;
0063   TMS570_ESM.SSR2   = 0xFFFFFFFFU;
0064   TMS570_ESM.SR[2U] = 0xFFFFFFFFU;
0065   TMS570_ESM.SR4    = 0xFFFFFFFFU;
0066
0067   /** - Setup LPC preload */
0068   TMS570_ESM.LTCPR = 16384U - 1U;
0069
0070   /** - Reset error pin */
0071   if (TMS570_ESM.EPSR == 0U) {
0072     /*
0073      * Per TMS570LC4x Errata DEVICE#60, the error pin cannot be cleared with a
0074      * normal EKR write upon system reset.  Put in diagnostic followed by
0075      * normal mode instead.  This sequence works also on other chip variants.
0076      */
0077     TMS570_ESM.EKR = 0x0000000AU;
0078     TMS570_ESM.EKR = 0x00000000U;
0079   }
0080
0081   /** - Clear interrupt level */
0082   TMS570_ESM.ILCR1 = 0xFFFFFFFFU;
0083   TMS570_ESM.ILCR4 = 0xFFFFFFFFU;
0084
0085   /** - Set interrupt level */
0086   TMS570_ESM.ILSR1 = 0x00000000;
0087
0088   TMS570_ESM.ILSR4 = 0x00000000;
0089
0090   /** - Enable error pin channels */
0091   TMS570_ESM.EEPAPR1 = 0x00000000;
0092
0093   TMS570_ESM.IEPSR4 = 0x00000000;
0094
0095   /** - Enable interrupts */
0096   TMS570_ESM.IESR1 = 0x00000000;
0097
0098   TMS570_ESM.IESR4 = 0x00000000;
0099 }