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0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This source file contains parts of the system initialization.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
0013  * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
0014  *
0015  *
0016  *  Redistribution and use in source and binary forms, with or without
0017  *  modification, are permitted provided that the following conditions
0018  *  are met:
0019  *
0020  *    Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  *
0023  *    Redistributions in binary form must reproduce the above copyright
0024  *    notice, this list of conditions and the following disclaimer in the
0025  *    documentation and/or other materials provided with the
0026  *    distribution.
0027  *
0028  *    Neither the name of Texas Instruments Incorporated nor the names of
0029  *    its contributors may be used to endorse or promote products derived
0030  *    from this software without specific prior written permission.
0031  *
0032  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0033  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0034  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0035  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0036  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0037  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0038  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0039  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0040  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0041  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0042  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0043  *
0044  */
0045 
0046 #include <bsp/tms570.h>
0047 #include <bsp/tms570_hwinit.h>
0048 #include <bsp/tms570-pinmux.h>
0049 
0050 enum tms570_system_clock_source {
0051   TMS570_SYS_CLK_SRC_OSC = 0U,          /**< Alias for oscillator clock Source                */
0052   TMS570_SYS_CLK_SRC_PLL1 = 1U,         /**< Alias for Pll1 clock Source                      */
0053   TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U,    /**< Alias for external clock Source                  */
0054   TMS570_SYS_CLK_SRC_LPO_LOW = 4U,      /**< Alias for low power oscillator low clock Source  */
0055   TMS570_SYS_CLK_SRC_LPO_HIGH = 5U,     /**< Alias for low power oscillator high clock Source */
0056   TMS570_SYS_CLK_SRC_PLL2 = 6U,         /**< Alias for Pll2 clock Source                      */
0057   TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U,    /**< Alias for external 2 clock Source                */
0058   TMS570_SYS_CLK_SRC_VCLK = 9U          /**< Alias for synchronous VCLK1 clock Source         */
0059 };
0060 
0061 /*
0062  * Definition of fuctions for all pins of TMS570LS3137.
0063  * This setup correctponds to TMS570LS31x HDK Kit
0064  */
0065 
0066 #define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \
0067   per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \
0068   per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \
0069   per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \
0070   per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \
0071   per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \
0072   per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \
0073   per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \
0074   per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \
0075   per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \
0076   per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \
0077   per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \
0078   per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \
0079   per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \
0080   per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \
0081   per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \
0082   per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \
0083   per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \
0084   per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \
0085   per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \
0086   per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \
0087   per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \
0088   per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \
0089   per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \
0090   per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \
0091   per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \
0092   per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \
0093   per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \
0094   per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \
0095   per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \
0096   per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \
0097   per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \
0098   per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \
0099   per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \
0100   per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \
0101   per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \
0102   per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \
0103   per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \
0104   per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \
0105   per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \
0106   per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \
0107   per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \
0108   per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \
0109   per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \
0110   per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \
0111   per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \
0112   per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \
0113   per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \
0114   per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \
0115   per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \
0116   per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \
0117   per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \
0118   per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \
0119   per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \
0120   per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \
0121   per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \
0122   per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \
0123   per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \
0124   per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \
0125   per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \
0126   per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \
0127   per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \
0128   per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \
0129   per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \
0130   per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \
0131   per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \
0132   per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \
0133   per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \
0134   per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \
0135   per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \
0136   per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \
0137   per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \
0138   per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \
0139   per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \
0140   per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \
0141   per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \
0142   per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \
0143   per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \
0144   per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \
0145   per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \
0146   per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \
0147   per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \
0148   per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \
0149   per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \
0150   per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \
0151   per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \
0152   per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \
0153   per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \
0154   per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \
0155   per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \
0156   per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \
0157   per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \
0158   per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \
0159   per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \
0160   per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \
0161   per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \
0162   per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \
0163   per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \
0164   per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \
0165   per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \
0166   per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \
0167   per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \
0168   per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \
0169   per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \
0170   per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \
0171   per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \
0172   per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \
0173   per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \
0174   per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \
0175   per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \
0176   per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \
0177   per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \
0178   per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \
0179   per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \
0180   per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \
0181   per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \
0182   per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \
0183   per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \
0184   per_pin_action( common_arg, \
0185   TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \
0186   per_pin_action( common_arg, \
0187   TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \
0188   per_pin_action( common_arg, \
0189   TMS570_MMR_SELECT_MII_MODE | TMS570_PIN_CLEAR_RQ_MASK ) \
0190   per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 )
0191 
0192 /*
0193  * The next construct allows to compute values for individual
0194  * PINMMR registers based on the multiple processing
0195  * complete pin functions list at compile time.
0196  * Each line computes 32-bit value which selects function
0197  * of consecutive four pins. Each pin function is defined
0198  * by single byte.
0199  */
0200 static const uint32_t tms570_pinmmr_init_data[] = {
0201   TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ),
0202   TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ),
0203   TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ),
0204   TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ),
0205   TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ),
0206   TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ),
0207   TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ),
0208   TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ),
0209   TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ),
0210   TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ),
0211   TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ),
0212   TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ),
0213   TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ),
0214   TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ),
0215   TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ),
0216   TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ),
0217   TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ),
0218   TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ),
0219   TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ),
0220   TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ),
0221   TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ),
0222   TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ),
0223   TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ),
0224   TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ),
0225   TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ),
0226   TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ),
0227   TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ),
0228   TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ),
0229   TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ),
0230   TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ),
0231   TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ),
0232 };
0233 
0234 /**
0235  * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit)
0236  */
0237 void tms570_pinmux_init( void )
0238 {
0239   tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0,
0240     RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) );
0241 
0242   /** - set ECLK pins functional mode */
0243   TMS570_SYS1.SYSPC1 = 0U;
0244 
0245   /** - set ECLK pins default output value */
0246   TMS570_SYS1.SYSPC4 = 0U;
0247 
0248   /** - set ECLK pins output direction */
0249   TMS570_SYS1.SYSPC2 = 1U;
0250 
0251   /** - set ECLK pins open drain enable */
0252   TMS570_SYS1.SYSPC7 = 0U;
0253 
0254   /** - set ECLK pins pullup/pulldown enable */
0255   TMS570_SYS1.SYSPC8 = 0U;
0256 
0257   /** - set ECLK pins pullup/pulldown select */
0258   TMS570_SYS1.SYSPC9 = 1U;
0259 
0260   /** - Setup ECLK */
0261   TMS570_SYS1.ECPCNTL = TMS570_SYS1_ECPCNTL_ECPSSEL * 0 |
0262                         TMS570_SYS1_ECPCNTL_ECPCOS * 0 |
0263                         TMS570_SYS1_ECPCNTL_ECPDIV( 8 - 1 );
0264 }
0265 
0266 void tms570_emif_sdram_init(void)
0267 {
0268   uint32_t dummy;
0269   uint32_t sdtimr = 0;
0270   uint32_t sdcr = 0;
0271 
0272   /* Do not run attempt to initialize SDRAM when code is running from it */
0273   if ( tms570_running_from_sdram() )
0274     return;
0275 
0276   sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 );
0277   sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 );
0278   sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 );
0279   sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 );
0280   sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 );
0281   sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 );
0282   sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 );
0283 
0284   TMS570_EMIF.SDTIMR = sdtimr;
0285 
0286   /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
0287   TMS570_EMIF.SDSRETR = 5;
0288   /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
0289   TMS570_EMIF.SDRCR = 2000;
0290 
0291   /* SR - Self-Refresh mode bit. */
0292   sdcr |= TMS570_EMIF_SDCR_SR * 0;
0293   /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */
0294   sdcr |= TMS570_EMIF_SDCR_PD * 0;
0295   /* PDWR - Perform refreshes during power down. */
0296   sdcr |= TMS570_EMIF_SDCR_PDWR * 0;
0297   /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */
0298   sdcr |= TMS570_EMIF_SDCR_NM * 1;
0299   /* CL - CAS Latency. */
0300   sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 );
0301   /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
0302   sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1;
0303   /* IBANK - Internal SDRAM Bank size. */
0304   sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */
0305   /* Page Size. This field defines the internal page size of connected SDRAM devices. */
0306   sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */
0307 
0308   TMS570_EMIF.SDCR = sdcr;
0309 
0310   dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN;
0311   (void) dummy;
0312   TMS570_EMIF.SDRCR = 31;
0313 
0314   /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
0315   TMS570_EMIF.SDRCR = 312;
0316 }
0317 
0318 /**
0319  * @brief Setup all system PLLs (HCG:setupPLL)
0320  *
0321  */
0322 void tms570_pll_init( void )
0323 {
0324   uint32_t pll12_dis = 0x42;
0325 
0326   /* Disable PLL1 and PLL2 */
0327   TMS570_SYS1.CSDISSET = pll12_dis;
0328 
0329   /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
0330   while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) {
0331     /* Wait */
0332   }
0333 
0334   /* Clear Global Status Register */
0335   TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP |
0336                         TMS570_SYS1_GLBSTAT_RFSLIP |
0337                         TMS570_SYS1_GLBSTAT_OSCFAIL;
0338   /** - Configure PLL control registers */
0339   /** @b Initialize @b Pll1: */
0340 
0341   /* Setup pll control register 1 */
0342   TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 |
0343                         TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) |
0344                         TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */
0345                         TMS570_SYS1_PLLCTL1_ROF * 0 |
0346                         TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) |
0347                         TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 );
0348 
0349   /* Setup pll control register 2 */
0350   TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 |
0351                         TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) |
0352                         TMS570_SYS1_PLLCTL2_MULMOD( 7 ) |
0353                         TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) |
0354                         TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 );
0355 
0356   /** @b Initialize @b Pll2: */
0357 
0358   /* Setup pll2 control register */
0359   TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) |
0360                         TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */
0361                         TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) |
0362                         TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 );
0363 
0364   /** - Enable PLL(s) to start up or Lock */
0365   TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */
0366                       0x00000000 | /* CLKSR1 on */
0367                       0x00000008 | /* CLKSR3 off */
0368                       0x00000000 | /* CLKSR4 on */
0369                       0x00000000 | /* CLKSR5 on */
0370                       0x00000000 | /* CLKSR6 on */
0371                       0x00000080;  /* CLKSR7 off */
0372 }
0373 
0374 /**
0375  * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks)
0376  *
0377  */
0378 /* SourceId : SYSTEM_SourceId_005 */
0379 /* DesignId : SYSTEM_DesignId_005 */
0380 /* Requirements : HL_SR469 */
0381 void tms570_map_clock_init( void )
0382 {
0383   uint32_t sys_csvstat, sys_csdis;
0384 
0385   /** @b Initialize @b Clock @b Tree: */
0386   /** - Disable / Enable clock domain */
0387   TMS570_SYS1.CDDIS = ( 0U << 4U ) |  /* AVCLK 1 OFF */
0388                       ( 0U << 5U ) |  /* AVCLK 2 OFF */
0389                       ( 0U << 8U ) |  /* VCLK3 OFF */
0390                       ( 0U << 9U ) |  /* VCLK4 OFF */
0391                       ( 1U << 10U ) | /* AVCLK 3 OFF */
0392                       ( 0U << 11U );  /* AVCLK 4 OFF */
0393 
0394   /* Work Around for Errata SYS#46:
0395    *
0396    * Errata Description:
0397    *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
0398    * Workaround:
0399    *            Always check the CSDIS register to make sure the clock source is turned on and check
0400    * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
0401    */
0402   /** - Wait for until clocks are locked */
0403   sys_csvstat = TMS570_SYS1.CSVSTAT;
0404   sys_csdis = TMS570_SYS1.CSDIS;
0405 
0406   while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
0407           ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
0408     sys_csvstat = TMS570_SYS1.CSVSTAT;
0409     sys_csdis = TMS570_SYS1.CSDIS;
0410   } /* Wait */
0411 
0412   /* Now the PLLs are locked and the PLL outputs can be sped up */
0413   /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
0414   TMS570_SYS1.PLLCTL1 =
0415     ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) |
0416     TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 );
0417   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
0418   TMS570_SYS2.PLLCTL3 =
0419     ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) |
0420     TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 );
0421 
0422   /* Enable/Disable Frequency modulation */
0423   TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA;
0424 
0425   /** - Map device clock domains to desired sources and configure top-level dividers */
0426   /** - All clock domains are working off the default clock sources until now */
0427   /** - The below assignments can be easily modified using the HALCoGen GUI */
0428 
0429   /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
0430   TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) |
0431                        TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) |
0432                        TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 );
0433 
0434   /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
0435   TMS570_SYS1.CLKCNTL =
0436     ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) |
0437     TMS570_SYS1_CLKCNTL_VCLK2R( 1 );
0438 
0439   TMS570_SYS1.CLKCNTL =
0440     ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) |
0441     TMS570_SYS1_CLKCNTL_VCLKR( 1 );
0442 
0443   TMS570_SYS2.CLK2CNTRL =
0444     ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) |
0445     TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 );
0446 
0447   TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) |
0448                           ( 1U << 8U ); /* FIXME: unknown in manual*/
0449 
0450   /** - Setup RTICLK1 and RTICLK2 clocks */
0451   TMS570_SYS1.RCLKSRC = ( 1U << 24U ) |
0452                         ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */
0453                         TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) |
0454                         TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK );
0455 
0456   /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
0457   TMS570_SYS1.VCLKASRC =
0458     TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) |
0459     TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK );
0460 
0461   TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) |
0462                           TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 |
0463                           TMS570_SYS2_VCLKACON1_VCLKA4S(
0464     TMS570_SYS_CLK_SRC_VCLK ) |
0465                           TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) |
0466                           TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 |
0467                           TMS570_SYS2_VCLKACON1_VCLKA3S(
0468     TMS570_SYS_CLK_SRC_VCLK );
0469 }
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