include/bsp/tms570_selftest.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides TMS570 selftest error codes, addresses and
0009  *   functions.
0010  */
0011
0012 /*
0013  * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
0014  *
0015  * Czech Technical University in Prague
0016  * Zikova 1903/4
0017  * 166 36 Praha 6
0018  * Czech Republic
0019  *
0020  * Algorithms are based on Ti manuals and Ti HalCoGen generated
0021  * code available under following copyright.
0022  *
0023  * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
0024  *
0025  *
0026  *  Redistribution and use in source and binary forms, with or without
0027  *  modification, are permitted provided that the following conditions
0028  *  are met:
0029  *
0030  *    Redistributions of source code must retain the above copyright
0031  *    notice, this list of conditions and the following disclaimer.
0032  *
0033  *    Redistributions in binary form must reproduce the above copyright
0034  *    notice, this list of conditions and the following disclaimer in the
0035  *    documentation and/or other materials provided with the
0036  *    distribution.
0037  *
0038  *    Neither the name of Texas Instruments Incorporated nor the names of
0039  *    its contributors may be used to endorse or promote products derived
0040  *    from this software without specific prior written permission.
0041  *
0042  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0043  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0044  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0045  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0046  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0047  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0048  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0049  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0050  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0051  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0052  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0053  *
0054  */
0055
0056 #ifndef LIBBSP_ARM_TMS570_SELFTEST_H
0057 #define LIBBSP_ARM_TMS570_SELFTEST_H
0058
0059 #include <stdint.h>
0060 #include <stdbool.h>
0061
0062 #define CCMSELFCHECK_FAIL1           1U
0063 #define CCMSELFCHECK_FAIL2           2U
0064 #define CCMSELFCHECK_FAIL3           3U
0065 #define CCMSELFCHECK_FAIL4           4U
0066 #define PBISTSELFCHECK_FAIL1         5U
0067 #define EFCCHECK_FAIL1               6U
0068 #define EFCCHECK_FAIL2               7U
0069 #define FMCECCCHECK_FAIL1            8U
0070 #define CHECKB0RAMECC_FAIL1          9U
0071 #define CHECKB1RAMECC_FAIL1         10U
0072 #define CHECKFLASHECC_FAIL1         11U
0073 #define VIMPARITYCHECK_FAIL1        12U
0074 #define DMAPARITYCHECK_FAIL1        13U
0075 #define HET1PARITYCHECK_FAIL1       14U
0076 #define HTU1PARITYCHECK_FAIL1       15U
0077 #define HET2PARITYCHECK_FAIL1       16U
0078 #define HTU2PARITYCHECK_FAIL1       17U
0079 #define ADC1PARITYCHECK_FAIL1       18U
0080 #define ADC2PARITYCHECK_FAIL1       19U
0081 #define CAN1PARITYCHECK_FAIL1       20U
0082 #define CAN2PARITYCHECK_FAIL1       21U
0083 #define CAN3PARITYCHECK_FAIL1       22U
0084 #define MIBSPI1PARITYCHECK_FAIL1    23U
0085 #define MIBSPI3PARITYCHECK_FAIL1    24U
0086 #define MIBSPI5PARITYCHECK_FAIL1    25U
0087 #define CHECKRAMECC_FAIL1           26U
0088 #define CHECKRAMECC_FAIL2           27U
0089 #define CHECKCLOCKMONITOR_FAIL1     28U
0090 #define CHECKFLASHEEPROMECC_FAIL1   29U
0091 #define CHECKFLASHEEPROMECC_FAIL2   31U
0092 #define CHECKFLASHEEPROMECC_FAIL3   32U
0093 #define CHECKFLASHEEPROMECC_FAIL4   33U
0094 #define CHECKPLL1SLIP_FAIL1         34U
0095 #define CHECKRAMADDRPARITY_FAIL1    35U
0096 #define CHECKRAMADDRPARITY_FAIL2    36U
0097 #define CHECKRAMUERRTEST_FAIL1      37U
0098 #define CHECKRAMUERRTEST_FAIL2      38U
0099 #define FMCBUS1PARITYCHECK_FAIL1    39U
0100 #define FMCBUS1PARITYCHECK_FAIL2    40U
0101 #define PBISTSELFCHECK_FAIL2         41U
0102 #define PBISTSELFCHECK_FAIL3         42U
0103
0104 /* PBIST and STC ROM - PBIST RAM GROUPING */
0105 #define PBIST_ROM_PBIST_RAM_GROUP   1U
0106 #define STC_ROM_PBIST_RAM_GROUP     2U
0107
0108 #define VIMRAMLOC       (*(volatile uint32_t *)0xFFF82000U)
0109 #define VIMRAMPARLOC    (*(volatile uint32_t *)0xFFF82400U)
0110
0111 #define NHET1RAMPARLOC  (*(volatile uint32_t *)0xFF462000U)
0112 #define NHET2RAMPARLOC  (*(volatile uint32_t *)0xFF442000U)
0113 #define adcPARRAM1      (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U))
0114 #define adcPARRAM2      (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U))
0115 #define canPARRAM1      (*(volatile uint32_t *)(0xFF1E0000U + 0x10U))
0116 #define canPARRAM2      (*(volatile uint32_t *)(0xFF1C0000U + 0x10U))
0117 #define canPARRAM3      (*(volatile uint32_t *)(0xFF1A0000U + 0x10U))
0118 #define HTU1PARLOC      (*(volatile uint32_t *)0xFF4E0200U)
0119 #define HTU2PARLOC      (*(volatile uint32_t *)0xFF4C0200U)
0120
0121 #define NHET1RAMLOC     (*(volatile uint32_t *)0xFF460000U)
0122 #define NHET2RAMLOC     (*(volatile uint32_t *)0xFF440000U)
0123 #define HTU1RAMLOC      (*(volatile uint32_t *)0xFF4E0000U)
0124 #define HTU2RAMLOC      (*(volatile uint32_t *)0xFF4C0000U)
0125
0126 #define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U)
0127 #define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U)
0128 #define canRAM1 (*(volatile uint32_t *)0xFF1E0000U)
0129 #define canRAM2 (*(volatile uint32_t *)0xFF1C0000U)
0130 #define canRAM3 (*(volatile uint32_t *)0xFF1A0000U)
0131
0132 #define DMARAMPARLOC    (*(volatile uint32_t *)(0xFFF80A00U))
0133 #define DMARAMLOC       (*(volatile uint32_t *)(0xFFF80000U))
0134
0135 #define MIBSPI1RAMLOC   (*(volatile uint32_t *)(0xFF0E0000U))
0136 #define MIBSPI3RAMLOC   (*(volatile uint32_t *)(0xFF0C0000U))
0137 #define MIBSPI5RAMLOC   (*(volatile uint32_t *)(0xFF0A0000U))
0138
0139 #define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U))
0140 #define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U))
0141 #define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U))
0142
0143 /** @enum pbistPort
0144  *   @brief Alias names for pbist Port number
0145  *
0146  *   This enumeration is used to provide alias names for the pbist Port number
0147  *     - PBIST_PORT0
0148  *     - PBIST_PORT1
0149  *
0150  *   @Note Check the datasheet for the port avaiability
0151  */
0152 enum pbistPort {
0153   PBIST_PORT0 = 0U,   /**< Alias for PBIST Port 0 */
0154   PBIST_PORT1 = 1U    /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */
0155 };
0156
0157 enum {
0158   PBIST_TripleReadSlow     = 0x00000001U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
0159   PBIST_TripleReadFast     = 0x00000002U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
0160   PBIST_March13N_DP        = 0x00000004U,  /**< March13 N Algo for 2 Port mem */
0161 };
0162
0163 uint32_t tms570_efc_check( void );
0164
0165 bool tms570_efc_check_self_test( void );
0166
0167 void bsp_selftest_fail_notification( uint32_t flag );
0168
0169 void tms570_memory_port0_fail_notification(
0170   uint32_t groupSelect,
0171   uint32_t dataSelect,
0172   uint32_t address,
0173   uint32_t data
0174 );
0175
0176 void tms570_esm_channel_sr_clear(
0177   unsigned grp,
0178   unsigned chan
0179 );
0180
0181 int tms570_esm_channel_sr_get(
0182   unsigned grp,
0183   unsigned chan
0184 );
0185
0186 void tms570_pbist_self_check( void );
0187
0188 void tms570_pbist_run(
0189   uint32_t raminfoL,
0190   uint32_t algomask
0191 );
0192
0193 bool tms570_pbist_is_test_completed( void );
0194
0195 bool tms570_pbist_is_test_passed( void );
0196
0197 void tms570_pbist_fail( void );
0198
0199 void tms570_pbist_stop( void );
0200
0201 void tms570_pbist_run_and_check( uint32_t raminfoL, uint32_t algomask );
0202
0203 void tms570_enable_parity( void );
0204
0205 void tms570_disable_parity( void );
0206
0207 bool tms570_efc_stuck_zero( void );
0208
0209 void tms570_efc_self_test( void );
0210
0211 bool tms570_pbist_port_test_status( uint32_t port );
0212
0213 void tms570_check_tcram_ecc( void );
0214
0215 #endif /*LIBBSP_ARM_TMS570_SELFTEST_H*/