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File indexing completed on 2025-05-11 08:23:39
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @ingroup RTEMSBSPsARMTMS570 0007 * 0008 * @brief This header file provides interfaces of the hardware initialization 0009 * support. 0010 */ 0011 0012 /* 0013 * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc 0014 * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> 0015 * 0016 * Google Summer of Code 2014 at 0017 * Czech Technical University in Prague 0018 * Zikova 1903/4 0019 * 166 36 Praha 6 0020 * Czech Republic 0021 * 0022 * Redistribution and use in source and binary forms, with or without 0023 * modification, are permitted provided that the following conditions 0024 * are met: 0025 * 1. Redistributions of source code must retain the above copyright 0026 * notice, this list of conditions and the following disclaimer. 0027 * 2. Redistributions in binary form must reproduce the above copyright 0028 * notice, this list of conditions and the following disclaimer in the 0029 * documentation and/or other materials provided with the distribution. 0030 * 0031 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 0032 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0033 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0034 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 0035 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0036 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0037 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0038 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0039 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0040 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0041 * POSSIBILITY OF SUCH DAMAGE. 0042 */ 0043 0044 #ifndef LIBBSP_ARM_TMS570_HWINIT_H 0045 #define LIBBSP_ARM_TMS570_HWINIT_H 0046 0047 #include <bspopts.h> 0048 #include <stdint.h> 0049 #include <bsp/start.h> 0050 0051 static inline bool tms570_running_from_tcram( void ) 0052 { 0053 uintptr_t fncptr = (uintptr_t)bsp_start_hook_0; 0054 return (fncptr - TMS570_MEMORY_SRAM_ORIGIN) < TMS570_MEMORY_SRAM_SIZE; 0055 } 0056 0057 static inline bool tms570_running_from_sdram( void ) 0058 { 0059 uintptr_t fncptr = (uintptr_t)bsp_start_hook_0; 0060 return (fncptr - TMS570_MEMORY_SDRAM_ORIGIN) < TMS570_MEMORY_SDRAM_SIZE; 0061 } 0062 0063 /* Ti TMS570 core setup implemented in assembly */ 0064 void _esmCcmErrorsClear_( void ); 0065 void _coreEnableEventBusExport_( void ); 0066 void _errata_CORTEXR4_66_( void ); 0067 void _errata_CORTEXR4_57_( void ); 0068 void _coreEnableRamEcc_( void ); 0069 void _coreDisableRamEcc_( void ); 0070 void _mpuInit_( void ); 0071 0072 void tms570_memory_init( uint32_t ram ); 0073 void tms570_trim_lpo_init( void ); 0074 void tms570_flash_init( void ); 0075 void tms570_periph_init( void ); 0076 void tms570_system_hw_init( void ); 0077 void tms570_esm_init( void ); 0078 0079 /* 0080 * The following functions that must be implemented on a per-board basis for 0081 * any BSP variant with hardware initialization. These configure MCU 0082 * peripherals that are specific to a particular board. 0083 */ 0084 0085 /** 0086 * @brief Initialize the External Memory InterFace (EMIF) peripheral. 0087 */ 0088 void tms570_emif_sdram_init(void); 0089 0090 /** 0091 * @brief Initialize PLLs source divider/multipliers. 0092 */ 0093 void tms570_pll_init(void); 0094 0095 /** 0096 * @brief Initialize the tms570 Global Clock Manager (GCM) registers which 0097 * sub-divide the input clock source (generally PLL) into the various 0098 * peripheral clocks (VCLK1-3, etc). 0099 */ 0100 void tms570_map_clock_init(void); 0101 0102 /** 0103 * @brief Initialize the tms570 PINMUX peripheral. This maps signals to pin 0104 * terminals. 0105 */ 0106 void tms570_pinmux_init(void); 0107 0108 #endif /* LIBBSP_ARM_TMS570_HWINIT_H */
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