bsp/ti_herc/reg_vim.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides VIM interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from VIM.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_VIM
0050 #define LIBBSP_ARM_TMS570_VIM
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t PARFLG;            /*Interrupt Vector Table Parity Flag Register*/
0056   uint32_t PARCTL;            /*Interrupt Vector Table Parity Control Register*/
0057   uint32_t ADDERR;            /*Address Parity Error Register*/
0058   uint32_t FBPARERR;          /*Fall-Back Address Parity Error Register*/
0059   uint8_t reserved1 [4];
0060   uint32_t IRQINDEX;          /*IRQ Index Offset Vector Register*/
0061   uint32_t FIQINDEX;          /*FIQ Index Offset Vector Register*/
0062   uint8_t reserved2 [8];
0063   uint32_t FIRQPR[3];         /*FIQ/IRQ Program Control Register*/
0064   uint8_t reserved3 [4];
0065   uint32_t INTREQ[3];         /*Pending Interrupt Read Location Register*/
0066   uint8_t reserved4 [4];
0067   uint32_t REQENASET[3];      /*Interrupt Enable Set Register */
0068   uint8_t reserved5 [4];
0069   uint32_t REQENACLR[3];      /*Interrupt Enable Clear Register */
0070   uint8_t reserved6 [4];
0071   uint32_t WAKEENASET[3];     /*Wake-Up Enable Set Register*/
0072   uint8_t reserved7 [4];
0073   uint32_t WAKEENACLR[3];     /*Wake-Up Enable Clear Registers*/
0074   uint8_t reserved8 [4];
0075   uint32_t IRQVECREG;         /*IRQ Interrupt Vector Register*/
0076   uint32_t FIQVECREG;         /*FIQ Interrupt Vector Register*/
0077   uint32_t CAPEVT;            /*Capture Event Register*/
0078   uint8_t reserved9 [4];
0079   uint32_t CHANCTRL[24];      /*VIM Interrupt Control Register*/
0080 } tms570_vim_t;
0081
0082
0083 /*---------------------TMS570_VIM_PARFLG---------------------*/
0084 /* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
0085 #define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0)
0086
0087
0088 /*---------------------TMS570_VIM_PARCTL---------------------*/
0089 /* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
0090 #define TMS570_VIM_PARCTL_TEST BSP_BIT32(8)
0091
0092 /* field: PARENA - VIM parity enable. */
0093 #define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
0094 #define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0095 #define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0096
0097
0098 /*---------------------TMS570_VIM_ADDERR---------------------*/
0099 /* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
0100 #define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
0101 #define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
0102 #define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
0103
0104 /* field: ADDERR - Address parity error register. */
0105 #define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
0106 #define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
0107 #define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
0108
0109 /* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
0110 #define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
0111 #define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
0112 #define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0113
0114
0115 /*--------------------TMS570_VIM_FBPARERR--------------------*/
0116 /* field: FBPARERR - Fall back address parity error. */
0117 /* Whole 32 bits */
0118
0119 /*--------------------TMS570_VIM_IRQINDEX--------------------*/
0120 /* field: IRQINDEX - IRQ index vector. */
0121 #define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
0122 #define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
0123 #define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0124
0125
0126 /*--------------------TMS570_VIM_FIQINDEX--------------------*/
0127 /* field: FIQINDEX - FIQ index offset vector. */
0128 #define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
0129 #define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
0130 #define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0131
0132
0133 /*---------------------TMS570_VIM_FIRQPR---------------------*/
0134 /* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
0135 /* Whole 32 bits */
0136
0137 /*---------------------TMS570_VIM_INTREQ---------------------*/
0138 /* field: INTREQx - Pending interrupt bits. 96 bit register. */
0139 /* Whole 32 bits */
0140
0141 /*--------------------TMS570_VIM_REQENASET--------------------*/
0142 /* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
0143 /* Whole 32 bits */
0144
0145 /*--------------------TMS570_VIM_REQENACLR--------------------*/
0146 /* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
0147 /* Whole 32 bits */
0148
0149 /*-------------------TMS570_VIM_WAKEENASET-------------------*/
0150 /* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
0151 /* Whole 32 bits */
0152
0153 /*-------------------TMS570_VIM_WAKEENACLR-------------------*/
0154 /* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
0155 /* Whole 32 bits */
0156
0157 /*--------------------TMS570_VIM_IRQVECREG--------------------*/
0158 /* field: IRQVECREG - IRQ interrupt vector register. */
0159 /* Whole 32 bits */
0160
0161 /*--------------------TMS570_VIM_FIQVECREG--------------------*/
0162 /* field: FIQVECREG - FIQ interrupt vector register. */
0163 /* Whole 32 bits */
0164
0165 /*---------------------TMS570_VIM_CAPEVT---------------------*/
0166 /* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
0167 #define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
0168 #define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
0169 #define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
0170
0171 /* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
0172 #define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
0173 #define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
0174 #define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
0175
0176
0177 /*--------------------TMS570_VIM_CHANCTRL--------------------*/
0178 /* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
0179 #define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
0180 #define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
0181 #define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
0182
0183 /* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
0184 #define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
0185 #define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
0186 #define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
0187
0188 /* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
0189 #define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
0190 #define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
0191 #define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
0192
0193 /* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
0194 #define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
0195 #define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
0196 #define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
0197
0198
0199
0200 #endif /* LIBBSP_ARM_TMS570_VIM */