bsp/ti_herc/reg_tcram.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides TCRAM interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from TCRAM.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_TCRAM
0050 #define LIBBSP_ARM_TMS570_TCRAM
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t RAMCTRL;           /*TCRAM Module Control Register*/
0056   uint32_t RAMTHRESHOLD;      /*TCRAM Module Single-Bit Error Correction Threshold Register*/
0057   uint32_t RAMOCCUR;          /*TCRAM Module Single-Bit Error Occurrences Control Register*/
0058   uint32_t RAMINTCTRL;        /*TCRAM Module Interrupt Control Register*/
0059   uint32_t RAMERRSTATUS;      /*TCRAM Module Error Status Register*/
0060   uint32_t RAMSERRADDR;       /*TCRAM Module Single-Bit Error Address Register*/
0061   uint8_t reserved1 [4];
0062   uint32_t RAMUERRADDR;       /*TCRAM Module Uncorrectable Error Address Register*/
0063   uint8_t reserved2 [16];
0064   uint32_t RAMTEST;           /*TCRAM Module Test Mode Control Register*/
0065   uint8_t reserved3 [4];
0066   uint32_t RAMADDRDECVECT;    /*TCRAM Module Test Mode Vector Register*/
0067   uint32_t RAMPERADDR;        /*TCRAM Module Parity Error Address Register*/
0068 } tms570_tcram_t;
0069
0070
0071 /*--------------------TMS570_TCRAM_RAMCTRL--------------------*/
0072 /* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
0073 #define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30)
0074
0075 /* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
0076 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
0077 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27)
0078 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0079
0080 /* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */
0081 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19)
0082 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19)
0083 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0084
0085 /* field: ECC_WR_EN - ECC Memory Write Enable. */
0086 #define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8)
0087
0088 /* field: ECC_DETECT_EN - ECC Detect Enable. */
0089 #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
0090 #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3)
0091 #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0092
0093
0094 /*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/
0095 /* field: THRESHOLD - Single-bit Error Threshold Count. */
0096 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
0097 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
0098 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0099
0100
0101 /*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/
0102 /* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
0103 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
0104 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
0105 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0106
0107
0108 /*------------------TMS570_TCRAM_RAMINTCTRL------------------*/
0109 /* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
0110 #define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0)
0111
0112
0113 /*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/
0114 /* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
0115 #define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9)
0116
0117 /* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
0118 #define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8)
0119
0120 /* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
0121 #define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5)
0122
0123 /* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
0124 #define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4)
0125
0126 /* field: ADDR_DEC_FAIL - Address decode failed. */
0127 #define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2)
0128
0129 /* field: SERR - Single Error Status. */
0130 #define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0)
0131
0132
0133 /*------------------TMS570_TCRAM_RAMSERRADDR------------------*/
0134 /* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
0135 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
0136 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
0137 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
0138
0139
0140 /*------------------TMS570_TCRAM_RAMUERRADDR------------------*/
0141 /* field: UNCORRECTABLE - address parity error. */
0142 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
0143 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
0144 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
0145
0146
0147 /*--------------------TMS570_TCRAM_RAMTEST--------------------*/
0148 /* field: TRIGGER - Test Trigger. */
0149 #define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8)
0150
0151 /* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
0152 #define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
0153 #define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7)
0154 #define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
0155
0156 /* field: TEST_ENABLE - Test Enable. */
0157 #define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3)
0158 #define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3)
0159 #define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0160
0161
0162 /*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/
0163 /* field: ECC_SELECT - ECC Select. */
0164 #define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26)
0165
0166 /* field: RAM_CHIP_SELECT - RAM Chip Select. */
0167 #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
0168 #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15)
0169 #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0170
0171
0172 /*------------------TMS570_TCRAM_RAMPERADDR------------------*/
0173 /* field: ADDRESS_PARITY - Parity Error Address. */
0174 #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
0175 #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
0176 #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
0177
0178
0179
0180 #endif /* LIBBSP_ARM_TMS570_TCRAM */