bsp/ti_herc/reg_sys2.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides SYS2 interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from SYS2.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_SYS2
0050 #define LIBBSP_ARM_TMS570_SYS2
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t PLLCTL3;           /*PLL Control Register 3*/
0056   uint8_t reserved1 [4];
0057   uint32_t STCCLKDIV;         /*CPU Logic BIST Clock Divider*/
0058   uint8_t reserved2 [24];
0059   uint32_t ECPCNTL;           /*ECP Control Register*/
0060   uint8_t reserved3 [20];
0061   uint32_t CLK2CNTRL;         /*Clock 2 Control Register*/
0062   uint32_t VCLKACON1;         /*Peripheral Asynchronous Clock Configuration 1 Register*/
0063   uint8_t reserved4 [16];
0064   uint32_t HCLKCNTL;          /* 0x0054 */
0065   uint8_t reserved5 [24];
0066   uint32_t CLKSLIP;           /*Clock Slip Register*/
0067   uint8_t reserved6 [120];
0068   uint32_t EFC_CTLREG;        /*EFUSE Controller Control Register*/
0069   uint32_t DIEDL_REG0;        /*Die Identification Register*/
0070   uint32_t DIEDH_REG1;        /*Die Identification Register*/
0071   uint32_t DIEDL_REG2;        /*Die Identification Register*/
0072   uint32_t DIEDH_REG3;        /*Die Identification Register*/
0073 } tms570_sys2_t;
0074
0075
0076 /*--------------------TMS570_SYS2_PLLCTL3--------------------*/
0077 /* field: ODPLL2 - Internal PLL Output Divider */
0078 #define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
0079 #define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
0080 #define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
0081
0082 /* field: PLLDIV2 - PLL2 Output Clock Divider */
0083 #define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
0084 #define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
0085 #define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0086
0087 /* field: REFCLKDIV2 - REFCLKDIV2 */
0088 #define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
0089 #define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
0090 #define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0091
0092 /* field: PLLMUL2 - PLL2 Multiplication Factor */
0093 #define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
0094 #define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
0095 #define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0096
0097
0098 /*-------------------TMS570_SYS2_STCCLKDIV-------------------*/
0099 /* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
0100 #define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
0101 #define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
0102 #define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
0103
0104
0105 /*--------------------TMS570_SYS2_ECPCNTL--------------------*/
0106 /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
0107 #define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_BIT32(24)
0108
0109 /* field: ECPCOS - ECP continue on suspend. */
0110 #define TMS570_SYS2_ECPCNTL_ECPCOS BSP_BIT32(23)
0111
0112 /* field: ECPINSEL - Select ECP input clock source. */
0113 #define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
0114 #define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
0115 #define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
0116
0117 /* field: ECPDIV - ECP divider value. */
0118 #define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
0119 #define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
0120 #define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0121
0122
0123 /*-------------------TMS570_SYS2_CLK2CNTRL-------------------*/
0124 /* field: VCLK3R - VBUS clock3 ratio. */
0125 #define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
0126 #define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
0127 #define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0128
0129
0130 /*-------------------TMS570_SYS2_VCLKACON1-------------------*/
0131 /* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
0132 #define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
0133 #define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
0134 #define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
0135
0136 /* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
0137 #define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_BIT32(20)
0138
0139 /* field: VCLKA4S - Peripheral asynchronous clock4 source. */
0140 #define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
0141 #define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19)
0142 #define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0143
0144 /* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */
0145 #define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10)
0146 #define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10)
0147 #define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0148
0149 /* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
0150 #define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_BIT32(4)
0151
0152 /* field: VCLKA3S - Peripheral asynchronous clock3 source. */
0153 #define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
0154 #define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3)
0155 #define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0156
0157
0158 /*--------------------TMS570_SYS2_CLKSLIP--------------------*/
0159 /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
0160 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
0161 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
0162 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
0163
0164 /* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
0165 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
0166 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
0167 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0168
0169
0170 /*-------------------TMS570_SYS2_EFC_CTLREG-------------------*/
0171 /* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
0172 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
0173 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
0174 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0175
0176
0177 /*-----------------------TMS570_SYS2_x-----------------------*/
0178 /* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
0179 /* Whole 32 bits */
0180
0181
0182 #endif /* LIBBSP_ARM_TMS570_SYS2 */