bsp/ti_herc/reg_sys.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides SYS interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from SYS.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_SYS1
0050 #define LIBBSP_ARM_TMS570_SYS1
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t SYSPC1;            /*SYS Pin Control Register 1*/
0056   uint32_t SYSPC2;            /*SYS Pin Control Register 2*/
0057   uint32_t SYSPC3;            /*SYS Pin Control Register 3*/
0058   uint32_t SYSPC4;            /*SYS Pin Control Register 4*/
0059   uint32_t SYSPC5;            /*SYS Pin Control Register 5*/
0060   uint32_t SYSPC6;            /*SYS Pin Control Register 6*/
0061   uint32_t SYSPC7;            /*SYS Pin Control Register 7*/
0062   uint32_t SYSPC8;            /*SYS Pin Control Register 8*/
0063   uint32_t SYSPC9;            /*SYS Pin Control Register 9*/
0064   uint8_t reserved1 [12];
0065   uint32_t CSDIS;             /*Clock Source Disable Register*/
0066   uint32_t CSDISSET;          /*Clock Source Disable Set Register*/
0067   uint32_t CSDISCLR;          /*Clock Source Disable Clear Register*/
0068   uint32_t CDDIS;             /*Clock Domain Disable Register*/
0069   uint32_t CDDISSET;          /*Clock Domain Disable Set Register*/
0070   uint32_t CDDISCLR;          /*Clock Domain Disable Clear Register*/
0071   uint32_t GHVSRC;            /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/
0072   uint32_t VCLKASRC;          /*Peripheral Asynchronous Clock Source Register*/
0073   uint32_t RCLKSRC;           /*RTI Clock Source Register*/
0074   uint32_t CSVSTAT;           /*Clock Source Valid Status Register*/
0075   uint32_t MSTGCR;            /*Memory Self-Test Global Control Register*/
0076   uint32_t MINITGCR;          /*Memory Hardware Initialization Global Control Register*/
0077   uint32_t MSIENA;            /*Memory Self-Test/Initialization Enable Register*/
0078   uint8_t reserved2 [4];
0079   uint32_t MSTCGSTAT;         /*MSTC Global Status Register*/
0080   uint32_t MINISTAT;          /*Memory Hardware Initialization Status Register*/
0081   uint32_t PLLCTL1;           /*PLL Control Register 1*/
0082   uint32_t PLLCTL2;           /*PLL Control Register 2*/
0083   uint32_t SYSPC10;           /*SYS Pin Control Register 10*/
0084   uint32_t DIEIDL;            /*Die Identification Register, Lower Word*/
0085   uint32_t DIEIDH;            /*Die Identification Register, Upper Word*/
0086   uint8_t reserved3 [4];
0087   uint32_t LPOMONCTL;         /*LPO/Clock Monitor Control Register*/
0088   uint32_t CLKTEST;           /*Clock Test Register*/
0089   uint32_t DFTCTRLREG1;       /*DFT Control Register*/
0090   uint32_t DFTCTRLREG2;       /*DFT Control Register 2*/
0091   uint8_t reserved4 [8];
0092   uint32_t GPREG1;            /*General Purpose Register*/
0093   uint8_t reserved5 [4];
0094   uint32_t IMPFASTS;          /*Imprecise Fault Status Register*/
0095   uint32_t IMPFTADD;          /*Imprecise Fault Write Address Register*/
0096   uint32_t SSIR1;             /*System Software Interrupt Request 1 Register*/
0097   uint32_t SSIR2;             /*System Software Interrupt Request 2 Register*/
0098   uint32_t SSIR3;             /*System Software Interrupt Request 3 Register*/
0099   uint32_t SSIR4;             /*System Software Interrupt Request 4 Register*/
0100   uint32_t RAMGCR;            /*RAM Control Register*/
0101   uint32_t BMMCR1;            /*Bus Matrix Module Control Register 1*/
0102   uint8_t reserved6 [4];
0103   uint32_t CPURSTCR;          /*CPU Reset Control Register*/
0104   uint32_t CLKCNTL;           /*Clock Control Register*/
0105   uint32_t ECPCNTL;           /*ECP Control Register*/
0106   uint8_t reserved7 [4];
0107   uint32_t DEVCR1;            /*DEV Parity Control Register 1*/
0108   uint32_t SYSECR;            /*System Exception Control Register*/
0109   uint32_t SYSESR;            /*System Exception Status Register*/
0110   uint32_t SYSTASR;           /*System Test Abort Status Register*/
0111   uint32_t GLBSTAT;           /*Global Status Register*/
0112   uint32_t DEVID;             /*Device Identification Register*/
0113   uint32_t SSIVEC;            /*Software Interrupt Vector Register*/
0114   uint32_t SSIF;              /*System Software Interrupt Flag Register*/
0115 } tms570_sys1_t;
0116
0117
0118 /*---------------------TMS570_SYS1_SYSPCx---------------------*/
0119 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
0120 #define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0)
0121
0122
0123 /*---------------------TMS570_SYS1_CSDIS---------------------*/
0124 /* field: CLKSROFF - Clock source[7-0] off. 2 reserved */
0125 #define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 7)
0126 #define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 7)
0127 #define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0128
0129 /* Clock Source 0                    Oscillator */
0130 #define TMS570_SYS1_CSDIS_CLKSR_OSC_NUM       0
0131 #define TMS570_SYS1_CSDIS_CLKSROFF_OSC        BSP_BIT32(0)
0132
0133 /* Clock Source 1                      PLL1 */
0134 #define TMS570_SYS1_CSDIS_CLKSR_PLL1_NUM      1
0135 #define TMS570_SYS1_CSDIS_CLKSROFF_PLL1       BSP_BIT32(1)
0136
0137 /* Clock Source 3                  EXTCLKIN */
0138 #define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN_NUM  3
0139 #define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN   BSP_BIT32(3)
0140
0141 /* Clock Source 4 Low Frequency LPO (Low Power Oscillator) clock */
0142 #define TMS570_SYS1_CSDIS_CLKSR_LPO_NUM       4
0143 #define TMS570_SYS1_CSDIS_CLKSROFF_LPO        BSP_BIT32(4)
0144
0145 /* Clock Source 5 High Frequency LPO (Low Power Oscillator) clock */
0146 #define TMS570_SYS1_CSDIS_CLKSR_HPO_NUM       5
0147 #define TMS570_SYS1_CSDIS_CLKSROFF_HPO        BSP_BIT32(5)
0148
0149 /* Clock Source 6                      PLL2 */
0150 #define TMS570_SYS1_CSDIS_CLKSR_PLL2_NUM      6
0151 #define TMS570_SYS1_CSDIS_CLKSROFF_PLL2       BSP_BIT32(6)
0152
0153 /* Clock Source 7                  EXTCLKIN2 */
0154 #define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN2_NUM 7
0155 #define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN2  BSP_BIT32(7)
0156
0157 /*--------------------TMS570_SYS1_CSDISSET--------------------*/
0158 /* field: SETCLKSR_OFF - Set clock source[7-0] to the disabled state. */
0159 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 7)
0160 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
0161 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0162
0163 /*--------------------TMS570_SYS1_CSDISCLR--------------------*/
0164 /* field: CLRCLKSR_OFF - Enables clock source[7-0] */
0165 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 7)
0166 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
0167 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0168
0169 /*---------------------TMS570_SYS1_CDDIS---------------------*/
0170 /* field: VCLKAOFF - VCLKA4 domain off. */
0171 #define TMS570_SYS1_CDDIS_VCLKAOFF4 BSP_BIT32(11)
0172
0173 /* field: VCLKAOFF - VCLKA3 domain off. */
0174 #define TMS570_SYS1_CDDIS_VCLKAOFF3 BSP_BIT32(10)
0175
0176 /* field: VCLK3OFF - VCLK3 domain off. */
0177 #define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8)
0178
0179 /* field: RTICLK1OFF - RTICLK1 domain off. */
0180 #define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6)
0181
0182 /* field: VCLKAOFF - VCLKA2 domain off. */
0183 #define TMS570_SYS1_CDDIS_VCLKAOFF2 BSP_BIT32(5)
0184
0185 /* field: VCLKAOFF - VCLKA1 domain off. */
0186 #define TMS570_SYS1_CDDIS_VCLKAOFF1 BSP_BIT32(4)
0187
0188 /* field: VCLK2OFF - VCLK2 domain off. */
0189 #define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3)
0190
0191 /* field: VCLKPOFF - VCLK_periph domain off. */
0192 #define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2)
0193
0194 /* field: HCLKOFF - HCLK and VCLK_sys domains off. */
0195 #define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1)
0196
0197 /* field: GCLKOFF - GCLK domain off. */
0198 #define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0)
0199
0200
0201 /*--------------------TMS570_SYS1_CDDISSET--------------------*/
0202 /* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
0203 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
0204 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
0205 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
0206
0207 /* field: SETVCLK3OFF - Set VCLK3 domain. */
0208 #define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8)
0209
0210 /* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
0211 #define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6)
0212
0213 /* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
0214 #define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5)
0215
0216 /* field: SETVCLKA1OFF - Set VCLKA1 domain. */
0217 #define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4)
0218
0219 /* field: SETVCLK2OFF - Set VCLK2 domain. */
0220 #define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3)
0221
0222 /* field: SETVCLKPOFF - Set VCLK_periph domain. */
0223 #define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2)
0224
0225 /* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
0226 #define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1)
0227
0228 /* field: SETGCLKOFF - Set GCLK domain. */
0229 #define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0)
0230
0231
0232 /*--------------------TMS570_SYS1_CDDISCLR--------------------*/
0233 /* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
0234 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
0235 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
0236 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
0237
0238 /* field: Reserved - Reserved */
0239 #define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9)
0240
0241 /* field: CLRVCLK3OFF - Clear VCLK3 domain. */
0242 #define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8)
0243
0244 /* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
0245 #define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6)
0246
0247 /* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
0248 #define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5)
0249
0250 /* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
0251 #define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4)
0252
0253 /* field: CLRVCLK2OFF - Clear VCLK2 domain. */
0254 #define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3)
0255
0256 /* field: CLRVCLKPOFF - CLRVCLKPOFF */
0257 #define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2)
0258
0259 /* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
0260 #define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1)
0261
0262 /* field: CLRGCLKOFF - Clear GCLK domain. */
0263 #define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0)
0264
0265
0266 /*---------------------TMS570_SYS1_GHVSRC---------------------*/
0267 /* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
0268 #define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
0269 #define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
0270 #define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0271
0272 /* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */
0273 #define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19)
0274 #define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19)
0275 #define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0276
0277 /* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */
0278 #define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3)
0279 #define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
0280 #define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0281
0282
0283 /*--------------------TMS570_SYS1_VCLKASRC--------------------*/
0284 /* field: VCLKA2S - Peripheral asynchronous clock2 source. */
0285 #define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
0286 #define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
0287 #define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0288
0289 /* field: VCLKA1S - Peripheral asynchronous clock1 source. */
0290 #define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3)
0291 #define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3)
0292 #define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0293
0294
0295 /*--------------------TMS570_SYS1_RCLKSRC--------------------*/
0296 /* field: RTI1DIV - RTI clock1 Divider. */
0297 #define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
0298 #define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
0299 #define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0300
0301 /* field: RTI1SRC - RTI clock1 source. */
0302 #define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3)
0303 #define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3)
0304 #define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0305
0306
0307 /*--------------------TMS570_SYS1_CSVSTAT--------------------*/
0308 /* field: CLKSRV - Clock source[7-0] valid. */
0309 #define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
0310 #define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
0311 #define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0312
0313 /* field: CLKSR - Clock source[1-0] valid. */
0314 #define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1)
0315 #define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1)
0316 #define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0317
0318
0319 /*---------------------TMS570_SYS1_MSTGCR---------------------*/
0320 /* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
0321 #define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
0322 #define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
0323 #define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0324
0325 /* field: MSTGENA - Memory self-test controller global enable key */
0326 #define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3)
0327 #define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0328 #define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0329
0330
0331 /*--------------------TMS570_SYS1_MINITGCR--------------------*/
0332 /* field: MINITGENA - Memory hardware initialization global enable key. */
0333 #define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
0334 #define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0335 #define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0336
0337
0338 /*---------------------TMS570_SYS1_MSIENA---------------------*/
0339 /* field: MSIENA - PBIST controller and memory initialization enable register. */
0340 /* Whole 32 bits */
0341
0342 /*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/
0343 /* field: MINIDONE - Memory hardware initialization complete status. */
0344 #define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8)
0345
0346 /* field: MSTDONE - Memory self-test run complete status. */
0347 #define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0)
0348
0349
0350 /*--------------------TMS570_SYS1_MINISTAT--------------------*/
0351 /* field: MIDONE - Memory hardware initialization status bit. */
0352 /* Whole 32 bits */
0353
0354 /*--------------------TMS570_SYS1_PLLCTL1--------------------*/
0355 /* field: ROS - Reset on PLL Slip */
0356 #define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
0357
0358 /* field: BPOS - Bypass of PLL Slip */
0359 #define TMS570_SYS1_PLLCTL1_BPOS(val) BSP_FLD32(val,29, 30)
0360 #define TMS570_SYS1_PLLCTL1_BPOS_GET(reg) BSP_FLD32GET(reg,29, 30)
0361 #define TMS570_SYS1_PLLCTL1_BPOS_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0362
0363 /* field: MASK_SLIP - Mask detection of PLL slip */
0364 #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
0365 #define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
0366 #define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0367
0368 /* field: PLLDIV - PLL Output Clock Divider */
0369 #define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
0370 #define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
0371 #define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0372
0373 /* field: ROF - Reset on Oscillator Fail */
0374 #define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23)
0375
0376 /* field: REFCLKDIV - Reference Clock Divider */
0377 #define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
0378 #define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
0379 #define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0380
0381 /* field: PLLMUL - PLL Multiplication Factor */
0382 #define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
0383 #define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
0384 #define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0385
0386
0387 /*--------------------TMS570_SYS1_PLLCTL2--------------------*/
0388 /* field: FMENA - Frequency Modulation Enable. */
0389 #define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31)
0390
0391 /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
0392 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
0393 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
0394 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
0395
0396 /* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
0397 #define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
0398 #define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
0399 #define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
0400
0401 /* field: ODPLL - Internal PLL Output Divider. */
0402 #define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
0403 #define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
0404 #define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
0405
0406 /* field: SPR_AMOUNT - Spreading Amount. */
0407 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
0408 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
0409 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0410
0411
0412 /*--------------------TMS570_SYS1_PLLCTL3--------------------*/
0413 /* field: ODPLL2 - Internal PLL Output Divider. */
0414 #define TMS570_SYS1_PLLCTL3_ODPLL2(val) BSP_FLD32(val, 29, 31)
0415 #define TMS570_SYS1_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg, 29, 31)
0416 #define TMS570_SYS1_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val, 29, 31)
0417
0418 /* field: PLLDIV2 - PLL2 Output Clock Divider. */
0419 #define TMS570_SYS1_PLLCTL3_PLLDIV2(val) BSP_FLD32(val, 24, 28)
0420 #define TMS570_SYS1_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg, 24, 28)
0421 #define TMS570_SYS1_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 24, 28)
0422
0423 /* field: REFCLKDIV2 - Reference Clock Divider. */
0424 #define TMS570_SYS1_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val, 16, 21)
0425 #define TMS570_SYS1_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg, 16, 21)
0426 #define TMS570_SYS1_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val, 16, 21)
0427
0428 /* field: PLLMUL2 - PLL2 Multiplication Factor. */
0429 #define TMS570_SYS1_PLLCTL3_PLLMUL2(val) BSP_FLD32(val, 0, 15)
0430 #define TMS570_SYS1_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg, 0, 15)
0431 #define TMS570_SYS1_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val, 0, 15)
0432
0433
0434 /*--------------------TMS570_SYS1_SYSPC10--------------------*/
0435 /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
0436 #define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
0437
0438
0439 /*---------------------TMS570_SYS1_DIEIDL---------------------*/
0440 /* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
0441 #define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
0442 #define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
0443 #define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31)
0444
0445 /* field: WAFER - These read only bits contain the wafer number of the device. */
0446 #define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21)
0447 #define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21)
0448 #define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0449
0450 /* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */
0451 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15)
0452 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15)
0453 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0454
0455 /* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */
0456 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7)
0457 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7)
0458 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0459
0460
0461 /*---------------------TMS570_SYS1_DIEIDH---------------------*/
0462 /* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
0463 #define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
0464 #define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
0465 #define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
0466
0467
0468 /*-------------------TMS570_SYS1_LPOMONCTL-------------------*/
0469 /* field: BIAS_ENABLE - Bias enable. */
0470 #define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
0471
0472 /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
0473 #define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
0474
0475 /* field: HFTRIM - High frequency oscillator trim value. */
0476 #define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
0477 #define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
0478 #define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
0479
0480
0481 /*--------------------TMS570_SYS1_CLKTEST--------------------*/
0482 /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
0483 #define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
0484
0485 /* field: RANGEDETCTRL - Range detection control. */
0486 #define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
0487
0488 /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
0489 #define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
0490
0491 /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
0492 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
0493 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
0494 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0495
0496 /* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */
0497 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11)
0498 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11)
0499 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0500
0501 /* field: SEL_ECP_PIN - ECLK pin clock source select */
0502 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3)
0503 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3)
0504 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0505
0506
0507 /*------------------TMS570_SYS1_DFTCTRLREG1------------------*/
0508 /* field: DFTWRITE - DFT logic access. */
0509 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
0510 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
0511 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
0512
0513 /* field: DFTREAD - DFT logic access. */
0514 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9)
0515 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9)
0516 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0517
0518 /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
0519 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
0520 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
0521 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0522
0523
0524 /*------------------TMS570_SYS1_DFTCTRLREG2------------------*/
0525 /* field: IMPDF - DFT Implementation defined bits. */
0526 #define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
0527 #define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
0528 #define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
0529
0530 /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
0531 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
0532 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
0533 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0534
0535
0536 /*---------------------TMS570_SYS1_GPREG1---------------------*/
0537 /* field: EMIF_FUNC - Enable EMIF functions to be output. */
0538 #define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31)
0539
0540 /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
0541 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
0542 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
0543 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0544
0545 /* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
0546 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
0547 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
0548 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0549
0550 /* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
0551 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
0552 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
0553 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0554
0555
0556 /*--------------------TMS570_SYS1_IMPFASTS--------------------*/
0557 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
0558 #define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0)
0559
0560
0561 /*--------------------TMS570_SYS1_IMPFTADD--------------------*/
0562 /* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
0563 /* Whole 32 bits */
0564
0565 /*---------------------TMS570_SYS1_SSIRx---------------------*/
0566 /* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
0567 #define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15)
0568 #define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
0569 #define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0570
0571 /* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
0572 #define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7)
0573 #define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
0574 #define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0575
0576
0577 /*---------------------TMS570_SYS1_RAMGCR---------------------*/
0578 /* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
0579 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
0580 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
0581 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0582
0583 /* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
0584 #define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2)
0585
0586 /* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
0587 #define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0)
0588
0589
0590 /*---------------------TMS570_SYS1_BMMCR1---------------------*/
0591 /* field: MEMSW - Memory swap key. */
0592 #define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
0593 #define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
0594 #define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0595
0596
0597 /*--------------------TMS570_SYS1_CPURSTCR--------------------*/
0598 /* field: CPU_RESET - CPU Reset. */
0599 #define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0)
0600
0601
0602 /*--------------------TMS570_SYS1_CLKCNTL--------------------*/
0603 /* field: VCLK2R - VBUS clock2 ratio. */
0604 #define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
0605 #define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
0606 #define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0607
0608 /* field: VCLKR - VBUS clock ratio. */
0609 #define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19)
0610 #define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19)
0611 #define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0612
0613 /* field: PENA - Peripheral enable bit. */
0614 #define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8)
0615
0616
0617 /*--------------------TMS570_SYS1_ECPCNTL--------------------*/
0618 /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
0619 #define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24)
0620
0621 /* field: ECPCOS - ECP continue on suspend. */
0622 #define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23)
0623
0624 /* field: ECPINSEL - Select ECP input clock source. */
0625 #define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
0626 #define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
0627 #define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
0628
0629 /* field: ECPDIV - ECP divider value. */
0630 #define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
0631 #define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
0632 #define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0633
0634
0635 /*---------------------TMS570_SYS1_DEVCR1---------------------*/
0636 /* field: DEVPARSEL - Device parity select bit key. */
0637 #define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
0638 #define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
0639 #define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0640
0641
0642 /*---------------------TMS570_SYS1_SYSECR---------------------*/
0643 /* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
0644 #define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
0645 #define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
0646 #define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
0647
0648
0649 /*---------------------TMS570_SYS1_SYSESR---------------------*/
0650 /* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
0651 #define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15)
0652
0653 /* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
0654 #define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14)
0655
0656 /* field: WDRST - Watchdog reset flag. */
0657 #define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
0658
0659 #if TMS570_VARIANT == 4357
0660
0661 /* field: DBGRST - Debug reset flag. */
0662 #define TMS570_SYS1_SYSESR_DBGRST BSP_BIT32(11)
0663
0664 /* field: ICSTRST - Interconnect reset flag. */
0665 #define TMS570_SYS1_SYSESR_ICSTRST BSP_BIT32(7)
0666
0667 #endif
0668
0669 /* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
0670 #define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
0671
0672 /* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
0673 #define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4)
0674
0675 /* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
0676 #define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3)
0677
0678 /* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
0679 #define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0)
0680
0681
0682 /*--------------------TMS570_SYS1_SYSTASR--------------------*/
0683 /* field: EFUSE_Abort - Test Abort status flag. */
0684 #define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
0685 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
0686 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0687
0688
0689 /*--------------------TMS570_SYS1_GLBSTAT--------------------*/
0690 /* field: FBSLIP - PLL over cycle slip detection. */
0691 #define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9)
0692
0693 /* field: RFSLIP - PLL under cycle slip detection. */
0694 #define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8)
0695
0696 /* field: OSCFAIL - Oscillator fail flag bit. */
0697 #define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0)
0698
0699
0700 /*---------------------TMS570_SYS1_DEVID---------------------*/
0701 /* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
0702 #define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31)
0703
0704 /* field: TECH - These bits define the process technology by which the device was manufactured. */
0705 #define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
0706 #define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16)
0707 #define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
0708
0709 /* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
0710 #define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12)
0711
0712 /* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
0713 #define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11)
0714
0715 /* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
0716 #define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
0717 #define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10)
0718 #define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
0719
0720 /* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
0721 #define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8)
0722
0723 /* field: VERSION - Version. These bits provide the revision of the device. */
0724 #define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
0725 #define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7)
0726 #define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0727
0728 /* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */
0729 #define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2)
0730 #define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2)
0731 #define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0732
0733
0734 /*---------------------TMS570_SYS1_SSIVEC---------------------*/
0735 /* field: SSIDATA - System software interrupt data key. */
0736 #define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
0737 #define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
0738 #define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0739
0740 /* field: SSIVECT - These bits contain the source for the system software interrupt. */
0741 #define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7)
0742 #define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7)
0743 #define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0744
0745
0746 /*----------------------TMS570_SYS1_SSIF----------------------*/
0747 /* field: SSI_FLAG - System software interrupt flag[4-1]. */
0748 #define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
0749 #define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
0750 #define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0751
0752
0753
0754 #endif /* LIBBSP_ARM_TMS570_SYS1 */