bsp/ti_herc/reg_stc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides STC interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from STC.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_STC
0050 #define LIBBSP_ARM_TMS570_STC
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t STCGCR0;           /*STC Global Control Register 0*/
0056   uint32_t STCGCR1;           /*STCGlobal Control Register 1*/
0057   uint32_t STCTPR;            /*Self-Test Run Timeout Counter Preload Register*/
0058   uint32_t STC_CADDR;         /*STC Current ROM Address Register*/
0059   uint32_t STCCICR;           /*STC Current Interval Count Register*/
0060   uint32_t STCGSTAT;          /*Self-Test Global Status Register*/
0061   uint32_t STCFSTAT;          /*Self-Test Fail Status Register*/
0062   uint32_t CPU1_CURMISR3;     /*CPU1 Current MISR Register 3*/
0063   uint32_t CPU1_CURMISR2;     /*CPU1 Current MISR Register 2*/
0064   uint32_t CPU1_CURMISR1;     /*CPU1 Current MISR Register 1*/
0065   uint32_t CPU1_CURMISR0;     /*CPU1 Current MISR Register 0*/
0066   uint32_t CPU2_CURMISR3;     /*CPU2 Current MISR Register 3*/
0067   uint32_t CPU2_CURMISR2;     /*CPU2 Current MISR Register 2*/
0068   uint32_t CPU2_CURMISR1;     /*CPU2 Current MISR Register 1*/
0069   uint32_t CPU2_CURMISR0;     /*CPU2 Current MISR Register 0*/
0070   uint32_t STCSCSCR;          /*Signature Compare Self-Check Register*/
0071 } tms570_stc_t;
0072
0073
0074 /*---------------------TMS570_STC_STCGCR0---------------------*/
0075 /* field: INTCOUNT - Number of intervals of self-test run */
0076 #define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
0077 #define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
0078 #define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0079
0080 /* field: RS_CNT - Restart or Continue */
0081 #define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0)
0082
0083
0084 /*---------------------TMS570_STC_STCGCR1---------------------*/
0085 /* field: STC_ENA - Self-test run enable key */
0086 #define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
0087 #define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0088 #define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0089
0090
0091 /*---------------------TMS570_STC_STCTPR---------------------*/
0092 /* field: RTOD - Self-test timeout count preload */
0093 /* Whole 32 bits */
0094
0095 /*--------------------TMS570_STC_STC_CADDR--------------------*/
0096 /* field: ADDR - Current ROM Address */
0097 /* Whole 32 bits */
0098
0099 /*---------------------TMS570_STC_STCCICR---------------------*/
0100 /* field: N - Interval Number */
0101 #define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
0102 #define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
0103 #define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0104
0105
0106 /*--------------------TMS570_STC_STCGSTAT--------------------*/
0107 /* field: TEST_FAIL - Test Fail */
0108 #define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1)
0109
0110 /* field: TEST_DONE - Test Done */
0111 #define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0)
0112
0113
0114 /*--------------------TMS570_STC_STCFSTAT--------------------*/
0115 /* field: TO_ERR - Timeout Error */
0116 #define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2)
0117
0118 /* field: CPU2_FAIL - CPU2 failure info */
0119 #define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1)
0120
0121 /* field: CPU1_FAIL - CPU1 failure info */
0122 #define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0)
0123
0124
0125 /*------------------TMS570_STC_CPU1_CURMISR3------------------*/
0126 /* field: MISR - MISR data from CPU1 */
0127 /* Whole 32 bits */
0128
0129 /*------------------TMS570_STC_CPU1_CURMISR2------------------*/
0130 /* field: MISR - MISR data from CPU1 */
0131 /* Whole 32 bits */
0132
0133 /*------------------TMS570_STC_CPU1_CURMISR1------------------*/
0134 /* field: MISR - MISR data from CPU1 */
0135 /* Whole 32 bits */
0136
0137 /*------------------TMS570_STC_CPU1_CURMISR0------------------*/
0138 /* field: MISR - MISR data from CPU1 */
0139 /* Whole 32 bits */
0140
0141 /*------------------TMS570_STC_CPU2_CURMISR3------------------*/
0142 /* field: MISR - MISR data from CPU2 */
0143 /* Whole 32 bits */
0144
0145 /*------------------TMS570_STC_CPU2_CURMISR2------------------*/
0146 /* field: MISR - MISR data from CPU2 */
0147 /* Whole 32 bits */
0148
0149 /*------------------TMS570_STC_CPU2_CURMISR1------------------*/
0150 /* field: MISR - MISR data from CPU2 */
0151 /* Whole 32 bits */
0152
0153 /*------------------TMS570_STC_CPU2_CURMISR0------------------*/
0154 /* field: MISR - MISR data from CPU2 */
0155 /* Whole 32 bits */
0156
0157 /*--------------------TMS570_STC_STCSCSCR--------------------*/
0158 /* field: FAULT_INS - Enable / Disable fault insertion. */
0159 #define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4)
0160
0161 /* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
0162 #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
0163 #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
0164 #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0165
0166
0167
0168 #endif /* LIBBSP_ARM_TMS570_STC */