bsp/ti_herc/reg_spi.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides SPI interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from SPI.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_SPI
0050 #define LIBBSP_ARM_TMS570_SPI
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t GCR0;              /*SPI Global Control Register 0*/
0056   uint32_t GCR1;              /*SPI Global Control Register 1*/
0057   uint32_t INT0;              /*SPI Interrupt Register*/
0058   uint32_t LVL;               /*SPI Interrupt Level Register*/
0059   uint32_t FLG;               /*SPI Flag Register*/
0060   uint32_t PC0;               /*SPI Pin Control Register 0*/
0061   uint32_t PC1;               /*SPI Pin Control Register 1*/
0062   uint32_t PC2;               /*SPI Pin Control Register 2*/
0063   uint32_t PC3;               /*SPI Pin Control Register 3*/
0064   uint32_t PC4;               /*SPI Pin Control Register 4*/
0065   uint32_t PC5;               /*SPI Pin Control Register 5*/
0066   uint32_t PC6;               /*SPI Pin Control Register 6*/
0067   uint32_t PC7;               /*SPI Pin Control Register 7*/
0068   uint32_t PC8;               /*SPI Pin Control Register 8*/
0069   uint32_t DAT0;              /*SPI Transmit Data Register 0*/
0070   uint32_t DAT1;              /*SPI Transmit Data Register 1*/
0071   uint32_t BUF;               /*SPI Receive Buffer Register*/
0072   uint32_t EMU;               /*SPI Emulation Register*/
0073   uint32_t DELAY;             /*SPI Delay Register*/
0074   uint32_t DEF;               /*SPI Default Chip Select Register*/
0075   uint32_t FMT0;              /*SPI Data Format Register 0*/
0076   uint32_t FMT1;              /*SPI Data Format Register 1*/
0077   uint32_t FMT2;              /*SPI Data Format Register 2*/
0078   uint32_t FMT3;              /*SPI Data Format Register 3*/
0079   uint32_t INTVECT0;          /*Interrupt Vector 0*/
0080   uint32_t INTVECT1;          /*Interrupt Vector 1*/
0081   uint8_t reserved1 [4];
0082   uint32_t PMCTRL;            /*Parallel/Modulo Mode Control Register*/
0083   uint32_t MIBSPIE;           /*Multi-buffer Mode Enable Register*/
0084   uint32_t TGITENST;          /*TG Interrupt Enable Set Register*/
0085   uint32_t TGITENCR;          /*TG Interrupt Enable Clear Register*/
0086   uint32_t TGITLVST;          /*Transfer Group Interrupt Level Set Register*/
0087   uint32_t TGITLVCR;          /*Transfer Group Interrupt Level Clear Register*/
0088   uint32_t TGINTFLG;          /*Transfer Group Interrupt Flag Register*/
0089   uint8_t reserved2 [8];
0090   uint32_t TICKCNT;           /*Tick Count Register*/
0091   uint32_t LTGPEND;           /*Last TG End Pointer*/
0092   uint32_t TGCTRL[16];        /*TG Control Registers*/
0093   uint32_t DMACTRL[8];        /*DMA Channel Control Register*/
0094   uint32_t DMACOUNT[8];       /*DMA COUNT Register*/
0095   uint32_t DMACNTLEN;         /*DMA Large Count*/
0096   uint8_t reserved3 [4];
0097   uint32_t UERRCTRL;          /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/
0098   uint32_t UERRSTAT;          /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/
0099   uint32_t UERRADDRRX;        /*RXRAM Uncorrectable Parity Error Address Register*/
0100   uint32_t UERRADDRTX;        /*TXRAM Uncorrectable Parity Error Address Register*/
0101   uint32_t RXOVRN_BUF_ADDR;   /*RXRAM Overrun Buffer Address Register*/
0102   uint32_t IOLPBKTSTCR;       /*I/O Loopback Test Control Register*/
0103   uint32_t EXT_PRESCALE1;     /*SPI Extended Prescale Register 1*/
0104   uint32_t EXT_PRESCALE2;     /*SPI Extended Prescale Register 2*/
0105 } tms570_spi_t;
0106
0107
0108 /*----------------------TMS570_SPI_GCR0----------------------*/
0109 /* field: nRESET - This is the local reset control for the module. */
0110 #define TMS570_SPI_GCR0_nRESET BSP_BIT32(0)
0111
0112
0113 /*----------------------TMS570_SPI_GCR1----------------------*/
0114 /* field: SPIEN - SPI enable. This bit enables SPI transfers. */
0115 #define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24)
0116
0117 /* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
0118 #define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16)
0119
0120 /* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
0121 #define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8)
0122
0123 /* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
0124 #define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1)
0125
0126 /* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
0127 #define TMS570_SPI_GCR1_MASTER BSP_BIT32(0)
0128
0129
0130 /*----------------------TMS570_SPI_INT0----------------------*/
0131 /* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
0132 #define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24)
0133
0134 /* field: DMAREQEN - DMA request enable. */
0135 #define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16)
0136
0137
0138 /*-----------------------TMS570_SPI_LVL-----------------------*/
0139 /* field: TXINTLVL - Transmit interrupt level. */
0140 #define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9)
0141
0142 /* field: RXINTLVL - Receive interrupt level. */
0143 #define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8)
0144
0145 /* field: RXOVRNINTLVL - Receive overrun interrupt level. */
0146 #define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6)
0147
0148 /* field: BITERRLVL - Bit error interrupt level. */
0149 #define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4)
0150
0151 /* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
0152 #define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3)
0153
0154 /* field: PARERRLVL - Parity error interrupt level. */
0155 #define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2)
0156
0157 /* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
0158 #define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1)
0159
0160 /* field: DLENERRLVL - Data length error interrupt level (line) select. */
0161 #define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0)
0162
0163
0164 /*-----------------------TMS570_SPI_FLG-----------------------*/
0165 /* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
0166 #define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24)
0167
0168 /* field: TXINTFLG - Transmitter-empty interrupt flag. */
0169 #define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9)
0170
0171 /* field: RXINTFLG - Receiver-full interrupt flag. */
0172 #define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8)
0173
0174 /* field: RXOVRNINTFLG - Receiver overrun flag. */
0175 #define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6)
0176
0177 /* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
0178 #define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4)
0179
0180 /* field: DESYNCFLG - Desynchronization of slave device. */
0181 #define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3)
0182
0183 /* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
0184 #define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2)
0185
0186 /* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
0187 #define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1)
0188
0189 /* field: DLENERRFLG - Data-length error flag. */
0190 #define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0)
0191
0192
0193 /*-----------------------TMS570_SPI_PC0-----------------------*/
0194 /* field: SOMIFUN - Slave out, master in function. */
0195 #define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
0196 #define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
0197 #define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0198
0199 /* field: SIMOFUN - Slave in, master out function. */
0200 #define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23)
0201 #define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23)
0202 #define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0203
0204 /* field: SOMIFUN0 - SOMIFUN0 */
0205 #define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11)
0206
0207 /* field: SIMOFUN0 - Slave in, master out function. */
0208 #define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10)
0209
0210 /* field: CLKFUN - CLKFUN */
0211 #define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9)
0212
0213 /* field: ENAFUN - SPIENA function. */
0214 #define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8)
0215
0216 /* field: SCSFUN - SPISCSx function. */
0217 #define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
0218 #define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7)
0219 #define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0220
0221
0222 /*-----------------------TMS570_SPI_PC1-----------------------*/
0223 /* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
0224 #define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
0225 #define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
0226 #define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0227
0228 /* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */
0229 #define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23)
0230 #define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23)
0231 #define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0232
0233 /* field: SOMIDIR0 - PISOMI0 direction. */
0234 #define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11)
0235
0236 /* field: SIMODIR0 - SPISIMO0 direction. */
0237 #define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10)
0238
0239 /* field: CLKDIR - SPICLK direction. */
0240 #define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9)
0241
0242 /* field: ENADIR - SPIENA direction. */
0243 #define TMS570_SPI_PC1_ENADIR BSP_BIT32(8)
0244
0245 /* field: SCSDIR - SPISCSx direction. */
0246 #define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
0247 #define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7)
0248 #define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0249
0250
0251 /*-----------------------TMS570_SPI_PC2-----------------------*/
0252 /* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
0253 #define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
0254 #define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
0255 #define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0256
0257 /* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */
0258 #define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23)
0259 #define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23)
0260 #define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0261
0262 /* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
0263 #define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11)
0264
0265 /* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
0266 #define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10)
0267
0268 /* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
0269 #define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9)
0270
0271 /* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
0272 #define TMS570_SPI_PC2_ENADIN BSP_BIT32(8)
0273
0274 /* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
0275 #define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
0276 #define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7)
0277 #define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0278
0279
0280 /*-----------------------TMS570_SPI_PC3-----------------------*/
0281 /* field: SOMIDOUT - SPISOMIx data out write. */
0282 #define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
0283 #define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
0284 #define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0285
0286 /* field: SIMODOUT - SPISIMOx data out write. */
0287 #define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23)
0288 #define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23)
0289 #define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0290
0291 /* field: SOMIDOUT0 - SPISOMI0 data out write. */
0292 #define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11)
0293
0294 /* field: SIMODOUT0 - SPISIMO0 data out write. */
0295 #define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10)
0296
0297 /* field: CLKDOUT - SPICLK data out write. */
0298 #define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9)
0299
0300 /* field: ENADOUT - SPIENA data out write. */
0301 #define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8)
0302
0303 /* field: SCSDOUT - SPISCSx data out write. */
0304 #define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
0305 #define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
0306 #define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0307
0308
0309 /*-----------------------TMS570_SPI_PC4-----------------------*/
0310 /* field: SOMISET - SPISOMIx data out set. */
0311 #define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
0312 #define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
0313 #define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0314
0315 /* field: SIMOSET - SPISIMOx data out set. */
0316 #define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23)
0317 #define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23)
0318 #define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0319
0320 /* field: SOMISET0 - SPISOMI0 data out set. */
0321 #define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11)
0322
0323 /* field: SIMOSET0 - purpose */
0324 #define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10)
0325
0326 /* field: CLKSET - SPICLK data out set. */
0327 #define TMS570_SPI_PC4_CLKSET BSP_BIT32(9)
0328
0329 /* field: ENASET - SPIENA data out set. */
0330 #define TMS570_SPI_PC4_ENASET BSP_BIT32(8)
0331
0332 /* field: SCSSET - SPISCSx data out set. */
0333 #define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
0334 #define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7)
0335 #define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0336
0337
0338 /*-----------------------TMS570_SPI_PC5-----------------------*/
0339 /* field: SOMICLR - SPISOMIx data out clear. */
0340 #define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
0341 #define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
0342 #define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0343
0344 /* field: SIMOCLR - SPISIMOx data out clear. */
0345 #define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23)
0346 #define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23)
0347 #define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0348
0349 /* field: SOMICLR0 - SPISOMI0 data out cleart. */
0350 #define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11)
0351
0352 /* field: SIMOCLR0 - SPISIMO0 data out clear. */
0353 #define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10)
0354
0355 /* field: CLKCLR - SPICLK data out clear. */
0356 #define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9)
0357
0358 /* field: ENACLR - SPIENA data out clear. */
0359 #define TMS570_SPI_PC5_ENACLR BSP_BIT32(8)
0360
0361 /* field: SCSCLR - SPISCSx data out clear. */
0362 #define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
0363 #define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
0364 #define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0365
0366
0367 /*-----------------------TMS570_SPI_PC6-----------------------*/
0368 /* field: SOMIPDR - SPISOMIx open drain enable. */
0369 #define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
0370 #define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
0371 #define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0372
0373 /* field: SIMOPDR - SPISIMOx open drain enable. */
0374 #define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23)
0375 #define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23)
0376 #define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0377
0378 /* field: SOMIPDR0 - SOMI0 open-drain enable. */
0379 #define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11)
0380
0381 /* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
0382 #define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10)
0383
0384 /* field: CLKPDR - CLK open drain enable. */
0385 #define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9)
0386
0387 /* field: ENAPDR - SPIENA pin open drain enable. */
0388 #define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8)
0389
0390 /* field: SCSPDR - SPISCSx open drain enable. */
0391 #define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
0392 #define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7)
0393 #define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0394
0395
0396 /*-----------------------TMS570_SPI_PC7-----------------------*/
0397 /* field: SOMIDIS - SOMIx pull control enable/disable. */
0398 #define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
0399 #define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
0400 #define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0401
0402 /* field: SIMODIS - SIMOx pull control enable/disable. */
0403 #define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23)
0404 #define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23)
0405 #define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0406
0407 /* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
0408 #define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11)
0409
0410 /* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
0411 #define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10)
0412
0413 /* field: CLKPDIS - CLK pull control enable/disable. */
0414 #define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9)
0415
0416 /* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
0417 #define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8)
0418
0419 /* field: SCSPDIS - SCSx pull control enable/disable. */
0420 #define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
0421 #define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
0422 #define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0423
0424
0425 /*-----------------------TMS570_SPI_PC8-----------------------*/
0426 /* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
0427 #define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
0428 #define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
0429 #define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0430
0431 /* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */
0432 #define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23)
0433 #define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23)
0434 #define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0435
0436 /* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
0437 #define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11)
0438
0439 /* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
0440 #define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10)
0441
0442 /* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
0443 #define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9)
0444
0445 /* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
0446 #define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8)
0447
0448 /* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
0449 #define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
0450 #define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7)
0451 #define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0452
0453
0454 /*----------------------TMS570_SPI_DAT0----------------------*/
0455 /* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
0456 #define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
0457 #define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
0458 #define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0459
0460
0461 /*----------------------TMS570_SPI_DAT1----------------------*/
0462 /* field: CSHOLD - Chip select hold mode. */
0463 #define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28)
0464
0465 /* field: WDEL - Enable the delay counter at the end of the current transaction. */
0466 #define TMS570_SPI_DAT1_WDEL BSP_BIT32(26)
0467
0468 /* field: DFSEL - Data word format select */
0469 #define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
0470 #define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25)
0471 #define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
0472
0473 /* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */
0474 #define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23)
0475 #define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
0476 #define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0477
0478 /* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */
0479 #define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15)
0480 #define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
0481 #define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0482
0483
0484 /*-----------------------TMS570_SPI_BUF-----------------------*/
0485 /* field: RXEMPTY - Receive data buffer empty. */
0486 #define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31)
0487
0488 /* field: RXOVR - Receive data buffer overrun. */
0489 #define TMS570_SPI_BUF_RXOVR BSP_BIT32(30)
0490
0491 /* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
0492 #define TMS570_SPI_BUF_TXFULL BSP_BIT32(29)
0493
0494 /* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
0495 #define TMS570_SPI_BUF_BITERR BSP_BIT32(28)
0496
0497 /* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
0498 #define TMS570_SPI_BUF_DESYNC BSP_BIT32(27)
0499
0500 /* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
0501 #define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26)
0502
0503 /* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
0504 #define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25)
0505
0506 /* field: DLENERR - Data length error flag. */
0507 #define TMS570_SPI_BUF_DLENERR BSP_BIT32(24)
0508
0509 /* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
0510 #define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
0511 #define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
0512 #define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0513
0514 /* field: RXDATA - SPI receive data. */
0515 #define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15)
0516 #define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
0517 #define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0518
0519
0520 /*-----------------------TMS570_SPI_EMU-----------------------*/
0521 /* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
0522 #define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
0523 #define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
0524 #define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0525
0526
0527 /*----------------------TMS570_SPI_DELAY----------------------*/
0528 /* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
0529 #define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
0530 #define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
0531 #define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0532
0533 /* field: T2CDELAY - T2CDELAY */
0534 #define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23)
0535 #define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23)
0536 #define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0537
0538 /* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */
0539 #define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15)
0540 #define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15)
0541 #define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0542
0543 /* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */
0544 #define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7)
0545 #define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7)
0546 #define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0547
0548
0549 /*-----------------------TMS570_SPI_DEF-----------------------*/
0550 /* field: CDEF - Chip select default pattern. Master-mode only. */
0551 #define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
0552 #define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
0553 #define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0554
0555
0556 /*----------------------TMS570_SPI_FMTx----------------------*/
0557 /* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
0558 #define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31)
0559 #define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
0560 #define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0561
0562 /* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
0563 #define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23)
0564
0565 /* field: PARITYENA - Parity enable for data format x. */
0566 #define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22)
0567
0568 /* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
0569 #define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21)
0570
0571 /* field: SHIFTDIR - Shift direction for data format x. */
0572 #define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20)
0573
0574 /* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
0575 #define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19)
0576
0577 /* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
0578 #define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18)
0579
0580 /* field: POLARITY - POLARITY */
0581 #define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17)
0582
0583 /* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
0584 #define TMS570_SPI_FMTx_PHASE BSP_BIT32(16)
0585
0586 /* field: PRESCALE - SPI data format x prescaler. */
0587 #define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15)
0588 #define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
0589 #define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0590
0591 /* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
0592 #define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4)
0593 #define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
0594 #define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0595
0596
0597 /*--------------------TMS570_SPI_INTVECT0--------------------*/
0598 /* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
0599 #define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
0600 #define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
0601 #define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
0602
0603 /* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
0604 #define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0)
0605
0606
0607 /*--------------------TMS570_SPI_INTVECT1--------------------*/
0608 /* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
0609 #define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
0610 #define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
0611 #define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
0612
0613 /* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
0614 #define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0)
0615
0616
0617 /*---------------------TMS570_SPI_PMCTRL---------------------*/
0618 /* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
0619 #define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29)
0620
0621 /* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
0622 #define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
0623 #define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28)
0624 #define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28)
0625
0626 /* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
0627 #define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25)
0628 #define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25)
0629 #define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
0630
0631 /* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
0632 #define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21)
0633
0634 /* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
0635 #define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
0636 #define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20)
0637 #define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20)
0638
0639 /* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
0640 #define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17)
0641 #define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17)
0642 #define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
0643
0644 /* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
0645 #define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13)
0646
0647 /* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
0648 #define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
0649 #define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12)
0650 #define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12)
0651
0652 /* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
0653 #define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9)
0654 #define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9)
0655 #define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0656
0657 /* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
0658 #define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5)
0659
0660 /* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
0661 #define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
0662 #define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4)
0663 #define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4)
0664
0665 /* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
0666 #define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1)
0667 #define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1)
0668 #define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0669
0670
0671 /*---------------------TMS570_SPI_MIBSPIE---------------------*/
0672 /* field: RXRAM_ACCESS - Receive-RAM access control. */
0673 #define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16)
0674
0675 /* field: MSPIENA - Multi-buffer mode enable. */
0676 #define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0)
0677
0678
0679 /*--------------------TMS570_SPI_TGITENST--------------------*/
0680 /* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
0681 #define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
0682 #define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
0683 #define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0684
0685 /* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */
0686 #define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15)
0687 #define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
0688 #define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0689
0690
0691 /*--------------------TMS570_SPI_TGITENCR--------------------*/
0692 /* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
0693 #define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
0694 #define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
0695 #define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0696
0697 /* field: CLR_INTENSUS - CLR INTENSUS */
0698 #define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15)
0699 #define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
0700 #define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0701
0702
0703 /*--------------------TMS570_SPI_TGITLVST--------------------*/
0704 /* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
0705 #define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
0706 #define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
0707 #define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0708
0709 /* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */
0710 #define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15)
0711 #define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
0712 #define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0713
0714
0715 /*--------------------TMS570_SPI_TGITLVCR--------------------*/
0716 /* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
0717 #define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
0718 #define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
0719 #define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0720
0721 /* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */
0722 #define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15)
0723 #define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
0724 #define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0725
0726
0727 /*--------------------TMS570_SPI_TGINTFLG--------------------*/
0728 /* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
0729 #define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
0730 #define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
0731 #define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0732
0733 /* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */
0734 #define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15)
0735 #define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
0736 #define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0737
0738
0739 /*---------------------TMS570_SPI_TICKCNT---------------------*/
0740 /* field: TICKENA - Tick counter enable. */
0741 #define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31)
0742
0743 /* field: RELOAD - Pre-load the tick counter. */
0744 #define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30)
0745
0746 /* field: CLKCTRL - Tick counter clock source control. */
0747 #define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
0748 #define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29)
0749 #define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
0750
0751 /* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */
0752 #define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15)
0753 #define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15)
0754 #define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0755
0756
0757 /*---------------------TMS570_SPI_LTGPEND---------------------*/
0758 /* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
0759 #define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
0760 #define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
0761 #define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0762
0763 /* field: LPEND - Last TG end pointer. */
0764 #define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14)
0765 #define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14)
0766 #define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
0767
0768
0769 /*---------------------TMS570_SPI_TGCTRL---------------------*/
0770 /* field: TGENA - TGx enable. */
0771 #define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31)
0772
0773 /* field: ONESHOTx - Single transfer for TGx. */
0774 #define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30)
0775
0776 /* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
0777 #define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29)
0778
0779 /* field: TGTDx - TG triggered. */
0780 #define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28)
0781
0782
0783 /*---------------------TMS570_SPI_DMACTRL---------------------*/
0784 /* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
0785 #define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31)
0786
0787 /* field: BUFIDx - Buffer utilized for DMA transfer. */
0788 #define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
0789 #define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30)
0790 #define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
0791
0792 /* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
0793 #define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23)
0794 #define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23)
0795 #define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
0796
0797 /* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
0798 #define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19)
0799 #define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19)
0800 #define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0801
0802 /* field: RXDMAENAx - Receive data DMA channel enable. */
0803 #define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15)
0804
0805 /* field: TXDAMENAx - Transmit data DMA channel enable. */
0806 #define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14)
0807
0808 /* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
0809 #define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13)
0810
0811 /* field: ICOUNTx - Initial count of DMA transfers. */
0812 #define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
0813 #define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12)
0814 #define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
0815
0816 /* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
0817 #define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6)
0818
0819 /* field: COUNTx - Actual number of remaining DMA transfers. */
0820 #define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
0821 #define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5)
0822 #define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0823
0824
0825 /*--------------------TMS570_SPI_DMACOUNT--------------------*/
0826 /* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
0827 #define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
0828 #define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
0829 #define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
0830
0831 /* field: COUNTx - The actual number of remaining DMA transfers. */
0832 #define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15)
0833 #define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15)
0834 #define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0835
0836
0837 /*--------------------TMS570_SPI_DMACNTLEN--------------------*/
0838 /* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
0839 #define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0)
0840
0841
0842 /*--------------------TMS570_SPI_UERRCTRL--------------------*/
0843 /* field: PTESTEN - Parity memory test enable. */
0844 #define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8)
0845
0846 /* field: EDEN - Error detection enable. These bits enable parity error detection. */
0847 #define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
0848 #define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3)
0849 #define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0850
0851
0852 /*--------------------TMS570_SPI_UERRSTAT--------------------*/
0853 /* field: EDFLG1 - RXRAM. */
0854 #define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1)
0855
0856 /* field: EDFLG0 - Uncorrectable parity error detection flag. */
0857 #define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0)
0858
0859
0860 /*-------------------TMS570_SPI_UERRADDRRX-------------------*/
0861 /* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
0862 #define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
0863 #define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
0864 #define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0865
0866
0867 /*-------------------TMS570_SPI_UERRADDRTX-------------------*/
0868 /* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
0869 #define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
0870 #define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
0871 #define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0872
0873
0874 /*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/
0875 /* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
0876 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
0877 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
0878 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0879
0880
0881 /*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/
0882 /* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
0883 #define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24)
0884
0885 /* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
0886 #define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20)
0887
0888 /* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
0889 #define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19)
0890
0891 /* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
0892 #define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18)
0893
0894 /* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
0895 #define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17)
0896
0897 /* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
0898 #define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16)
0899
0900 /* field: IOLPBKSTENA - Module I/O loopback test enable key. */
0901 #define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
0902 #define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
0903 #define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0904
0905 /* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */
0906 #define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5)
0907 #define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5)
0908 #define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
0909
0910 /* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
0911 #define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2)
0912
0913 /* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
0914 #define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1)
0915
0916 /* field: RXP_ENA - Enable analog loopback through the receive pin. */
0917 #define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0)
0918
0919
0920 /*------------------TMS570_SPI_EXT_PRESCALEx------------------*/
0921 /* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */
0922 #define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26)
0923 #define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26)
0924 #define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
0925
0926
0927
0928 #endif /* LIBBSP_ARM_TMS570_SPI */