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File indexing completed on 2025-05-11 08:23:39
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @ingroup RTEMSBSPsARMTMS570 0007 * 0008 * @brief This header file provides SCI interfaces. 0009 */ 0010 0011 /* The header file is generated by make_header.py from SCI.json */ 0012 /* Current script's version can be found at: */ 0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ 0014 0015 /* 0016 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> 0017 * 0018 * Czech Technical University in Prague 0019 * Zikova 1903/4 0020 * 166 36 Praha 6 0021 * Czech Republic 0022 * 0023 * All rights reserved. 0024 * 0025 * Redistribution and use in source and binary forms, with or without 0026 * modification, are permitted provided that the following conditions are met: 0027 * 0028 * 1. Redistributions of source code must retain the above copyright notice, this 0029 * list of conditions and the following disclaimer. 0030 * 2. Redistributions in binary form must reproduce the above copyright notice, 0031 * this list of conditions and the following disclaimer in the documentation 0032 * and/or other materials provided with the distribution. 0033 * 0034 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 0035 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 0036 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 0037 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 0038 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 0039 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 0040 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 0041 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 0042 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 0043 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0044 * 0045 * The views and conclusions contained in the software and documentation are those 0046 * of the authors and should not be interpreted as representing official policies, 0047 * either expressed or implied, of the FreeBSD Project. 0048 */ 0049 #ifndef LIBBSP_ARM_TMS570_SCI 0050 #define LIBBSP_ARM_TMS570_SCI 0051 0052 #include <bsp/utility.h> 0053 0054 typedef struct{ 0055 uint32_t GCR0; /*SCI Global Control Register 0*/ 0056 uint32_t GCR1; /*SCI Global Control Register 1*/ 0057 uint32_t GCR2; /*SCI Global Control Register 2*/ 0058 uint32_t SETINT; /*SCI Set Interrupt Register*/ 0059 uint32_t CLEARINT; /*SCI Clear Interrupt Register*/ 0060 uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/ 0061 uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/ 0062 uint32_t FLR; /*SCI Flags Register*/ 0063 uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/ 0064 uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/ 0065 uint32_t FORMAT; /*SCI Format Control Register*/ 0066 uint32_t BRS; /*Baud Rate Selection Register*/ 0067 uint32_t ED; /*Receiver Emulation Data Buffer*/ 0068 uint32_t RD; /*Receiver Data Buffer*/ 0069 uint32_t TD; /*Transmit Data Buffer*/ 0070 uint32_t PIO0; /*SCI Pin I/O Control Register 0*/ 0071 uint32_t PIO1; /*SCI Pin I/O Control Register 1*/ 0072 uint32_t PIO2; /*SCI Pin I/O Control Register 2*/ 0073 uint32_t PIO3; /*SCI Pin I/O Control Register 3*/ 0074 uint32_t PIO4; /*SCI Pin I/O Control Register 4*/ 0075 uint32_t PIO5; /*SCI Pin I/O Control Register 5*/ 0076 uint32_t PIO6; /*SCI Pin I/O Control Register 6*/ 0077 uint32_t PIO7; /*SCI Pin I/O Control Register 7*/ 0078 uint32_t PIO8; /*SCI Pin I/O Control Register 8*/ 0079 uint8_t reserved1 [48]; 0080 uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/ 0081 } tms570_sci_t; 0082 0083 0084 /*----------------------TMS570_SCI_GCR0----------------------*/ 0085 /* field: Reserved - Read returns 0. Writes have no effect. */ 0086 #define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31) 0087 #define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) 0088 #define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31) 0089 0090 /* field: RESET - This bit resets the SCI module. */ 0091 #define TMS570_SCI_GCR0_RESET BSP_BIT32(0) 0092 0093 0094 /*----------------------TMS570_SCI_GCR1----------------------*/ 0095 /* field: TXENA - Transmit enable. */ 0096 #define TMS570_SCI_GCR1_TXENA BSP_BIT32(25) 0097 0098 /* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */ 0099 #define TMS570_SCI_GCR1_RXENA BSP_BIT32(24) 0100 0101 /* field: CONT - Continue on suspend. */ 0102 #define TMS570_SCI_GCR1_CONT BSP_BIT32(17) 0103 0104 /* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */ 0105 #define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16) 0106 0107 /* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */ 0108 #define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9) 0109 0110 /* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */ 0111 #define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8) 0112 0113 /* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */ 0114 #define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7) 0115 0116 /* field: CLOCK - CLOCK */ 0117 #define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5) 0118 0119 /* field: STOP - SCI number of stop bits per frame. */ 0120 #define TMS570_SCI_GCR1_STOP BSP_BIT32(4) 0121 0122 /* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */ 0123 #define TMS570_SCI_GCR1_PARITY BSP_BIT32(3) 0124 0125 /* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */ 0126 #define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2) 0127 0128 /* field: TIMING_MODE - SCI timing mode bit. */ 0129 #define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1) 0130 0131 /* field: COMM_MODE - SCI communication mode bit. */ 0132 #define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0) 0133 0134 0135 /*----------------------TMS570_SCI_GCR2----------------------*/ 0136 /* field: CC - Compare checksum. LIN mode only. */ 0137 #define TMS570_SCI_GCR2_CC BSP_BIT32(17) 0138 0139 /* field: SC - Send checksum byte. This bit is effective in LIN mode only. */ 0140 #define TMS570_SCI_GCR2_SC BSP_BIT32(16) 0141 0142 /* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */ 0143 #define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8) 0144 0145 /* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */ 0146 #define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0) 0147 0148 0149 /*---------------------TMS570_SCI_SETINT---------------------*/ 0150 /* field: SET_FE_INT - */ 0151 #define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26) 0152 0153 /* field: SET_OE_INT - SET OE INT */ 0154 #define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25) 0155 0156 /* field: SET_PE_INT - Set parity interrupt. */ 0157 #define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24) 0158 0159 /* field: SET_RX_DMA_ALL - SET RX DMA ALL */ 0160 #define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) 0161 0162 /* field: SET_RX_DMA - SET RX DMA */ 0163 #define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17) 0164 0165 /* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */ 0166 #define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16) 0167 0168 /* field: SET_RX_INT - SET RX INT */ 0169 #define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9) 0170 0171 /* field: SET_TX_INT - Set transmitter interrupt. */ 0172 #define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8) 0173 0174 /* field: SET_WAKEUP_INT - Set wakeup interrupt. */ 0175 #define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1) 0176 0177 /* field: SET_BRKDT_INT - Set breakdetect interrupt. */ 0178 #define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0) 0179 0180 0181 /*--------------------TMS570_SCI_CLEARINT--------------------*/ 0182 /* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */ 0183 #define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26) 0184 0185 /* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */ 0186 #define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25) 0187 0188 /* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */ 0189 #define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24) 0190 0191 /* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */ 0192 #define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) 0193 0194 /* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */ 0195 #define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17) 0196 0197 /* field: CLR_TX_DMA - CLR TX DMA */ 0198 #define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16) 0199 0200 /* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */ 0201 #define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9) 0202 0203 /* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */ 0204 #define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8) 0205 0206 /* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */ 0207 #define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) 0208 0209 /* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */ 0210 #define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) 0211 0212 0213 /*--------------------TMS570_SCI_SETINTLVL--------------------*/ 0214 /* field: SET_FE_INT_LVL - Set framing-error interrupt level. */ 0215 #define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) 0216 0217 /* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */ 0218 #define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) 0219 0220 /* field: SET_PE_INT_LVL - Set parity error interrupt level. */ 0221 #define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) 0222 0223 /* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */ 0224 #define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) 0225 0226 /* field: SET_RX_INT_LVL - Set receiver interrupt level. */ 0227 #define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) 0228 0229 /* field: SET_TX_INT_LVL - Set transmitter interrupt level. */ 0230 #define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) 0231 0232 /* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */ 0233 #define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) 0234 0235 /* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */ 0236 #define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) 0237 0238 0239 /*-------------------TMS570_SCI_CLEARINTLVL-------------------*/ 0240 /* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */ 0241 #define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) 0242 0243 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */ 0244 #define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) 0245 0246 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */ 0247 #define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) 0248 0249 /* field: CLR_PE_INT_LVL - */ 0250 #define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) 0251 0252 /* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */ 0253 #define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) 0254 0255 /* field: CLR_RX_INT_LVL - Clear receiver interrupt. */ 0256 #define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) 0257 0258 /* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */ 0259 #define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8) 0260 0261 /* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */ 0262 #define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) 0263 0264 /* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */ 0265 #define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) 0266 0267 0268 /*-----------------------TMS570_SCI_FLR-----------------------*/ 0269 /* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */ 0270 #define TMS570_SCI_FLR_FE BSP_BIT32(26) 0271 0272 /* field: OE - Overrun error flag. */ 0273 #define TMS570_SCI_FLR_OE BSP_BIT32(25) 0274 0275 /* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */ 0276 #define TMS570_SCI_FLR_PE BSP_BIT32(24) 0277 0278 /* field: RXWAKE - Receiver wakeup detect flag. */ 0279 #define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12) 0280 0281 /* field: TX_EMPTY - Transmitter empty flag. */ 0282 #define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11) 0283 0284 /* field: TXWAKE - Transmitter wakeup method select. */ 0285 #define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10) 0286 0287 /* field: RXRDY - Receiver ready flag. */ 0288 #define TMS570_SCI_FLR_RXRDY BSP_BIT32(9) 0289 0290 /* field: TXRDY - Transmitter buffer register ready flag. */ 0291 #define TMS570_SCI_FLR_TXRDY BSP_BIT32(8) 0292 0293 /* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */ 0294 #define TMS570_SCI_FLR_BUSY BSP_BIT32(3) 0295 0296 /* field: IDLE - SCI receiver in idle state. */ 0297 #define TMS570_SCI_FLR_IDLE BSP_BIT32(2) 0298 0299 /* field: WAKEUP - Wakeup flag. */ 0300 #define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1) 0301 0302 /* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */ 0303 #define TMS570_SCI_FLR_BRKDT BSP_BIT32(0) 0304 0305 0306 /*--------------------TMS570_SCI_INTVECT0--------------------*/ 0307 /* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */ 0308 #define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) 0309 #define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) 0310 #define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) 0311 0312 0313 /*--------------------TMS570_SCI_INTVECT1--------------------*/ 0314 /* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */ 0315 #define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) 0316 #define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) 0317 #define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) 0318 0319 0320 /*---------------------TMS570_SCI_FORMAT---------------------*/ 0321 /* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */ 0322 #define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) 0323 #define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) 0324 #define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) 0325 0326 0327 /*-----------------------TMS570_SCI_BRS-----------------------*/ 0328 /* field: BAUD - SCI 24-bit baud selection. */ 0329 #define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23) 0330 #define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) 0331 #define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) 0332 0333 0334 /*-----------------------TMS570_SCI_ED-----------------------*/ 0335 /* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */ 0336 #define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7) 0337 #define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) 0338 #define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) 0339 0340 0341 /*-----------------------TMS570_SCI_RD-----------------------*/ 0342 /* field: RD - Receiver data. */ 0343 #define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7) 0344 #define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) 0345 #define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) 0346 0347 0348 /*-----------------------TMS570_SCI_TD-----------------------*/ 0349 /* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */ 0350 #define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7) 0351 #define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) 0352 #define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) 0353 0354 0355 /*----------------------TMS570_SCI_PIO0----------------------*/ 0356 /* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */ 0357 #define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2) 0358 0359 /* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */ 0360 #define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1) 0361 0362 0363 /*----------------------TMS570_SCI_PIO1----------------------*/ 0364 /* field: TX_DIR - Transmit pin direction. */ 0365 #define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2) 0366 0367 /* field: RX_DIR - Receive pin direction. */ 0368 #define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1) 0369 0370 0371 /*----------------------TMS570_SCI_PIO2----------------------*/ 0372 /* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */ 0373 #define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2) 0374 0375 /* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */ 0376 #define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1) 0377 0378 0379 /*----------------------TMS570_SCI_PIO3----------------------*/ 0380 /* field: TX_OUT - Transmit pin out. */ 0381 #define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2) 0382 0383 /* field: RX_OUT - Receive pin out. */ 0384 #define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1) 0385 0386 0387 /*----------------------TMS570_SCI_PIO4----------------------*/ 0388 /* field: TX_SET - Transmit pin set. */ 0389 #define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2) 0390 0391 /* field: RX_SET - Receive pin set. */ 0392 #define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1) 0393 0394 0395 /*----------------------TMS570_SCI_PIO5----------------------*/ 0396 /* field: TX_CLR - Transmit pin clear. */ 0397 #define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2) 0398 0399 /* field: RX_CLR - Receive pin clear. */ 0400 #define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1) 0401 0402 0403 /*----------------------TMS570_SCI_PIO6----------------------*/ 0404 /* field: TX_PDR - Transmit pin open drain enable. */ 0405 #define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2) 0406 0407 /* field: RX_PDR - Receive pin open drain enable. */ 0408 #define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1) 0409 0410 0411 /*----------------------TMS570_SCI_PIO7----------------------*/ 0412 /* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */ 0413 #define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2) 0414 0415 /* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */ 0416 #define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1) 0417 0418 0419 /*----------------------TMS570_SCI_PIO8----------------------*/ 0420 /* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */ 0421 #define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2) 0422 0423 /* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */ 0424 #define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1) 0425 0426 0427 /*--------------------TMS570_SCI_IODFTCTRL--------------------*/ 0428 /* field: FEN - Frame error enable. This bit is used to create a frame error. */ 0429 #define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26) 0430 0431 /* field: PEN - Parity error enable. This bit is used to create a parity error. */ 0432 #define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25) 0433 0434 /* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */ 0435 #define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24) 0436 0437 /* field: PIN_SAMPLE_MASK - Pin sample mask. */ 0438 #define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) 0439 #define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) 0440 #define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20) 0441 0442 /* field: TX_SHIFT - Transmit shift. */ 0443 #define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) 0444 #define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) 0445 #define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) 0446 0447 /* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */ 0448 #define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) 0449 #define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) 0450 #define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) 0451 0452 /* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */ 0453 #define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1) 0454 0455 /* field: RXPENA - Module analog loopback through receive pin enable. */ 0456 #define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0) 0457 0458 0459 0460 #endif /* LIBBSP_ARM_TMS570_SCI */
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