bsp/ti_herc/reg_rtp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides RTP interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from RTP.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_RTP
0050 #define LIBBSP_ARM_TMS570_RTP
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t GLBCTRL;           /*RTP Global Control Register*/
0056   uint32_t TRENA;             /*RTP Trace Enable Register*/
0057   uint32_t GSR;               /*RTP Global Status Register*/
0058   uint32_t RAM1REG1;          /*RTP RAM 1 Trace Region 1 Register*/
0059   uint32_t RAM1REG2;          /*RTP RAM 1 Trace Region 2 Register*/
0060   uint32_t RAM2REG1;          /*RTP RAM 2 Trace Region 1 Register*/
0061   uint32_t RAM2REG2;          /*RTP RAM 2 Trace Region 2 Register*/
0062   uint8_t reserved1 [8];
0063   uint32_t PERREG1;           /*RTP Peripheral Trace Region 1 Register*/
0064   uint32_t PERREG2;           /*RTP Peripheral Trace Region 2 Register*/
0065   uint32_t DDMW;              /*RTP Direct Data Mode Write Register*/
0066   uint8_t reserved2 [4];
0067   uint32_t PC0;               /*RTP Pin Control 0 Register*/
0068   uint32_t PC1;               /*RTP Pin Control 1 Register*/
0069   uint32_t PC2;               /*RTP Pin Control 2 Register*/
0070   uint32_t PC3;               /*RTP Pin Control 3 Register*/
0071   uint32_t PC4;               /*RTP Pin Control 4 Register*/
0072   uint32_t PC5;               /*RTP Pin Control 5 Register*/
0073   uint32_t PC6;               /*RTP Pin Control 6 Register*/
0074   uint32_t PC7;               /*RTP Pin Control 7 Register*/
0075   uint32_t PC8;               /*RTP Pin Control 8 Register*/
0076 } tms570_rtp_t;
0077
0078
0079 /*---------------------TMS570_RTP_GLBCTRL---------------------*/
0080 /* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */
0081 #define TMS570_RTP_GLBCTRL_TEST BSP_BIT32(24)
0082
0083 /* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */
0084 #define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18)
0085 #define TMS570_RTP_GLBCTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg,16, 18)
0086 #define TMS570_RTP_GLBCTRL_PRESCALER_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0087
0088 /* field: DDM_WIDTH - Direct data mode word size width. */
0089 #define TMS570_RTP_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,12, 13)
0090 #define TMS570_RTP_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,12, 13)
0091 #define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
0092
0093 /* field: DDM_RW -  */
0094 #define TMS570_RTP_GLBCTRL_DDM_RW BSP_BIT32(11)
0095
0096 /* field: TM_DDM - Trace Mode or Direct Data Mode */
0097 #define TMS570_RTP_GLBCTRL_TM_DDM BSP_BIT32(10)
0098
0099 /* field: PW - Port width. This bit field configures the RTP to the desired port width. */
0100 #define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9)
0101 #define TMS570_RTP_GLBCTRL_PW_GET(reg) BSP_FLD32GET(reg,8, 9)
0102 #define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0103
0104 /* field: RESET - This bit resets the state machine and the registers to their reset value. */
0105 #define TMS570_RTP_GLBCTRL_RESET BSP_BIT32(7)
0106
0107 /* field: CONTCLK - Continuous RTPCLK enable. */
0108 #define TMS570_RTP_GLBCTRL_CONTCLK BSP_BIT32(6)
0109
0110 /* field: HOVF - Halt on overflow. */
0111 #define TMS570_RTP_GLBCTRL_HOVF BSP_BIT32(5)
0112
0113 /* field: INV_RGN - Trace inside or outside of defined trace regions. */
0114 #define TMS570_RTP_GLBCTRL_INV_RGN BSP_BIT32(4)
0115
0116 /* field: ON_OFF - ON/Off switch. */
0117 #define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
0118 #define TMS570_RTP_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
0119 #define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0120
0121
0122 /*----------------------TMS570_RTP_TRENA----------------------*/
0123 /* field: ENA4 - Enable tracing for peripherals. */
0124 #define TMS570_RTP_TRENA_ENA4 BSP_BIT32(24)
0125
0126 /* field: ENA2 - Enable tracing for RAM block 2. */
0127 #define TMS570_RTP_TRENA_ENA2 BSP_BIT32(8)
0128
0129 /* field: ENA1 -  */
0130 #define TMS570_RTP_TRENA_ENA1 BSP_BIT32(0)
0131
0132
0133 /*-----------------------TMS570_RTP_GSR-----------------------*/
0134 /* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */
0135 #define TMS570_RTP_GSR_EMPTYSER BSP_BIT32(12)
0136
0137 /* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */
0138 #define TMS570_RTP_GSR_EMPTYPER BSP_BIT32(11)
0139
0140 /* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */
0141 #define TMS570_RTP_GSR_EMPTY2 BSP_BIT32(9)
0142
0143 /* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */
0144 #define TMS570_RTP_GSR_EMPTY1 BSP_BIT32(8)
0145
0146 /* field: OVFPER - Overflow peripheral FIFO. */
0147 #define TMS570_RTP_GSR_OVFPER BSP_BIT32(3)
0148
0149 /* field: OVF2 - Overflow RAM block 2 FIFO. */
0150 #define TMS570_RTP_GSR_OVF2 BSP_BIT32(1)
0151
0152 /* field: OVF1 - Overflow RAM block 1 FIFO. */
0153 #define TMS570_RTP_GSR_OVF1 BSP_BIT32(0)
0154
0155
0156 /*--------------------TMS570_RTP_RAM1REGx--------------------*/
0157 /* field: CPU_DMA - CPU and/or other master access. */
0158 #define TMS570_RTP_RAM1REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
0159 #define TMS570_RTP_RAM1REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
0160 #define TMS570_RTP_RAM1REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0161
0162 /* field: RW - Read/Write. */
0163 #define TMS570_RTP_RAM1REGx_RW BSP_BIT32(28)
0164
0165 /* field: BLOCKSIZE - These bits define the length of the trace region. */
0166 #define TMS570_RTP_RAM1REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
0167 #define TMS570_RTP_RAM1REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
0168 #define TMS570_RTP_RAM1REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0169
0170 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
0171 #define TMS570_RTP_RAM1REGx_STARTADDR(val) BSP_FLD32(val,0, 17)
0172 #define TMS570_RTP_RAM1REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
0173 #define TMS570_RTP_RAM1REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
0174
0175
0176 /*--------------------TMS570_RTP_RAM2REGx--------------------*/
0177 /* field: CPU_DMA - CPU and/or other master access. */
0178 #define TMS570_RTP_RAM2REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
0179 #define TMS570_RTP_RAM2REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
0180 #define TMS570_RTP_RAM2REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0181
0182 /* field: RW - Read/Write. */
0183 #define TMS570_RTP_RAM2REGx_RW BSP_BIT32(28)
0184
0185 /* field: BLOCKSIZE - These bits define the length of the trace region. */
0186 #define TMS570_RTP_RAM2REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
0187 #define TMS570_RTP_RAM2REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
0188 #define TMS570_RTP_RAM2REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0189
0190 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
0191 #define TMS570_RTP_RAM2REGx_STARTADDR(val) BSP_FLD32(val,0, 23)
0192 #define TMS570_RTP_RAM2REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
0193 #define TMS570_RTP_RAM2REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
0194
0195
0196 /*---------------------TMS570_RTP_PERREGx---------------------*/
0197 /* field: CPU_DMA - CPU and/or other master access. */
0198 #define TMS570_RTP_PERREGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
0199 #define TMS570_RTP_PERREGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
0200 #define TMS570_RTP_PERREGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0201
0202 /* field: RW - Read/Write. */
0203 #define TMS570_RTP_PERREGx_RW BSP_BIT32(28)
0204
0205 /* field: BLOCKSIZE - These bits define the length of the trace region. */
0206 #define TMS570_RTP_PERREGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
0207 #define TMS570_RTP_PERREGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
0208 #define TMS570_RTP_PERREGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0209
0210 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
0211 #define TMS570_RTP_PERREGx_STARTADDR(val) BSP_FLD32(val,0, 23)
0212 #define TMS570_RTP_PERREGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
0213 #define TMS570_RTP_PERREGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
0214
0215
0216 /*----------------------TMS570_RTP_DDMW----------------------*/
0217 /* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */
0218 /* Whole 32 bits */
0219
0220 /*-----------------------TMS570_RTP_PCx-----------------------*/
0221 /* field: ENAFUNC - Functional mode of RTPENA pin. */
0222 #define TMS570_RTP_PCx_ENAFUNC BSP_BIT32(18)
0223
0224 /* field: CLKFUNC - Functional mode of RTPCLK pin. */
0225 #define TMS570_RTP_PCx_CLKFUNC BSP_BIT32(17)
0226
0227 /* field: SYNCFUNC - Functional mode of RTPSYNC pin. */
0228 #define TMS570_RTP_PCx_SYNCFUNC BSP_BIT32(16)
0229
0230 /* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */
0231 #define TMS570_RTP_PCx_DATAFUNC(val) BSP_FLD32(val,0, 15)
0232 #define TMS570_RTP_PCx_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
0233 #define TMS570_RTP_PCx_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0234
0235
0236
0237 #endif /* LIBBSP_ARM_TMS570_RTP */