bsp/ti_herc/reg_rti.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides RTI interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from RTI.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_RTI
0050 #define LIBBSP_ARM_TMS570_RTI
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t COMPx;             /*RTI Compare x Register*/
0056   uint32_t UDCPx;             /*RTI Update Compare x Register*/
0057 } tms570_rti_compare_t;
0058
0059 typedef struct{
0060   uint32_t FRCx;              /*RTI Free Running Counter x Register*/
0061   uint32_t UCx;               /*RTI Up Counter x Register*/
0062   uint32_t CPUCx;             /*RTI Compare Up Counter x Register*/
0063   uint8_t reserved1 [4];
0064   uint32_t CAFRCx;            /*RTI Capture Free Running Counter x Register*/
0065   uint32_t CAUCx;             /*RTI Capture Up Counter x Register*/
0066   uint32_t rsvd[2];           /*Reserved*/
0067 } tms570_rti_counter_t;
0068
0069 typedef struct{
0070   uint32_t GCTRL;             /*RTI Global Control Register*/
0071   uint32_t TBCTRL;            /*RTI Timebase Control Register*/
0072   uint32_t CAPCTRL;           /*RTI Capture Control Register*/
0073   uint32_t COMPCTRL;          /*RTI Compare Control Register*/
0074   tms570_rti_counter_t CNT[2];/*Counters*/
0075   tms570_rti_compare_t CMP[4];/*Compares*/
0076   uint32_t TBLCOMP;           /*RTI Timebase Low Compare Register*/
0077   uint32_t TBHCOMP;           /*RTI Timebase High Compare Register*/
0078   uint8_t reserved2 [8];
0079   uint32_t SETINTENA;         /*RTI Set Interrupt Enable Register*/
0080   uint32_t CLEARINTENA;       /*RTI Clear Interrupt Enable Register*/
0081   uint32_t INTFLAG;           /*RTI Interrupt Flag Register*/
0082   uint8_t reserved3 [4];
0083   uint32_t DWDCTRL;           /*Digital Watchdog Control Register*/
0084   uint32_t DWDPRLD;           /*Digital Watchdog Preload Register*/
0085   uint32_t WDSTATUS;          /*Watchdog Status Register*/
0086   uint32_t WDKEY;             /*RTI Watchdog Key Register*/
0087   uint32_t DWDCNTR;           /*RTI Digital Watchdog Down Counter Register*/
0088   uint32_t WWDRXNCTRL;        /*Digital Windowed Watchdog Reaction Control Register*/
0089   uint32_t WWDSIZECTRL;       /*Digital Windowed Watchdog Window Size Control Register*/
0090   uint32_t INTCLRENABLE;      /*RTI Compare Interrupt Clear Enable Register*/
0091   uint32_t COMP0CLR;          /*RTI Compare 0 Clear Register*/
0092   uint32_t COMP1CLR;          /*RTI Compare 1 Clear Register*/
0093   uint32_t COMP2CLR;          /*RTI Compare 2 Clear Register*/
0094   uint32_t COMP3CLR;          /*RTI Compare 3 Clear Register*/
0095 } tms570_rti_t;
0096
0097
0098 /*----------------------TMS570_RTI_COMPx----------------------*/
0099 /* field: COMPx - Compare x. */
0100 /* Whole 32 bits */
0101
0102 /*----------------------TMS570_RTI_UDCPx----------------------*/
0103 /* field: UDCPx - Update compare x. */
0104 /* Whole 32 bits */
0105
0106 /*----------------------TMS570_RTI_FRCx----------------------*/
0107 /* field: FRC0 - FRC0 */
0108 /* Whole 32 bits */
0109
0110 /*-----------------------TMS570_RTI_UCx-----------------------*/
0111 /* field: UC0 - Up counter 0. */
0112 /* Whole 32 bits */
0113
0114 /*----------------------TMS570_RTI_CPUCx----------------------*/
0115 /* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
0116 /* Whole 32 bits */
0117
0118 /*---------------------TMS570_RTI_CAFRCx---------------------*/
0119 /* field: CAFRC0 - Capture free running counter 0. */
0120 /* Whole 32 bits */
0121
0122 /*----------------------TMS570_RTI_CAUCx----------------------*/
0123 /* field: CAUC0 - Capture up counter 0. */
0124 /* Whole 32 bits */
0125
0126 /*----------------------TMS570_RTI_rsvd----------------------*/
0127 /* field: CAUC0 - Capture up counter 0. */
0128 /* Whole 32 bits */
0129
0130 /*----------------------TMS570_RTI_GCTRL----------------------*/
0131 /* field: NTUSEL - Select NTU signal. */
0132 #define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
0133 #define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
0134 #define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0135
0136 /* field: COS - Continue on suspend. */
0137 #define TMS570_RTI_GCTRL_COS BSP_BIT32(15)
0138
0139 /* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
0140 #define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1)
0141
0142 /* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
0143 #define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0)
0144
0145
0146 /*---------------------TMS570_RTI_TBCTRL---------------------*/
0147 /* field: INC - Increment free running counter 0. */
0148 #define TMS570_RTI_TBCTRL_INC BSP_BIT32(1)
0149
0150 /* field: TBEXT - Timebase external. */
0151 #define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0)
0152
0153
0154 /*---------------------TMS570_RTI_CAPCTRL---------------------*/
0155 /* field: CAPCNTR1 - Capture counter 1. */
0156 #define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1)
0157
0158 /* field: CAPCNTR0 - Capture counter 0. */
0159 #define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0)
0160
0161
0162 /*--------------------TMS570_RTI_COMPCTRL--------------------*/
0163 /* field: COMPSEL3 - Compare select 3. */
0164 #define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12)
0165
0166 /* field: COMPSEL2 - Compare select 2. */
0167 #define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8)
0168
0169 /* field: COMPSEL1 - Compare select 1. */
0170 #define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4)
0171
0172 /* field: COMPSEL0 - Compare select 0. */
0173 #define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0)
0174
0175
0176 /*---------------------TMS570_RTI_TBLCOMP---------------------*/
0177 /* field: TBLCOMP - Timebase low compare value. */
0178 /* Whole 32 bits */
0179
0180 /*---------------------TMS570_RTI_TBHCOMP---------------------*/
0181 /* field: TBHCOMP - Timebase high compare value. */
0182 /* Whole 32 bits */
0183
0184 /*--------------------TMS570_RTI_SETINTENA--------------------*/
0185 /* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
0186 #define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18)
0187
0188 /* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
0189 #define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17)
0190
0191 /* field: SETTBINT - Set timebase interrupt. */
0192 #define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16)
0193
0194 /* field: SETDMA3 - Set compare DMA request 3. */
0195 #define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11)
0196
0197 /* field: SETDMA2 - Set compare DMA request 2. */
0198 #define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10)
0199
0200 /* field: SETDMA1 - Set compare DMA request 1. */
0201 #define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9)
0202
0203 /* field: SETDMA0 - Set compare DMA request 0. */
0204 #define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8)
0205
0206 /* field: SETINT3 - Set compare interrupt 3. */
0207 #define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3)
0208
0209 /* field: SETINT2 - Set compare interrupt 2. */
0210 #define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2)
0211
0212 /* field: SETINT1 - Set compare interrupt 1. */
0213 #define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1)
0214
0215 /* field: SETINT0 - Set compare interrupt 0. */
0216 #define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0)
0217
0218
0219 /*-------------------TMS570_RTI_CLEARINTENA-------------------*/
0220 /* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
0221 #define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18)
0222
0223 /* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
0224 #define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17)
0225
0226 /* field: CLEARTBINT - Clear timebase interrupt. */
0227 #define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16)
0228
0229 /* field: CLEARDMA3 - Clear compare DMA request 3. */
0230 #define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11)
0231
0232 /* field: CLEARDMA2 - Clear compare DMA request 2. */
0233 #define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10)
0234
0235 /* field: CLEARDMA1 - Clear compare DMA request 1. */
0236 #define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9)
0237
0238 /* field: CLEARDMA0 - Clear compare DMA request 0. */
0239 #define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8)
0240
0241 /* field: CLEARINT3 - Clear compare interrupt 3. */
0242 #define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3)
0243
0244 /* field: CLEARINT2 - Clear compare interrupt 2. */
0245 #define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2)
0246
0247 /* field: CLEARINT1 - Clear compare interrupt 1. */
0248 #define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1)
0249
0250 /* field: CLEARINT0 - Clear compare interrupt 0. */
0251 #define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0)
0252
0253
0254 /*---------------------TMS570_RTI_INTFLAG---------------------*/
0255 /* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
0256 #define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18)
0257
0258 /* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
0259 #define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17)
0260
0261 /* field: TBINT - Timebase interrupt flag. */
0262 #define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16)
0263
0264 /* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
0265 #define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3)
0266
0267 /* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
0268 #define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2)
0269
0270 /* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
0271 #define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1)
0272
0273 /* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
0274 #define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0)
0275
0276
0277 /*---------------------TMS570_RTI_DWDCTRL---------------------*/
0278 /* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
0279 /* Whole 32 bits */
0280
0281 /*---------------------TMS570_RTI_DWDPRLD---------------------*/
0282 /* field: DWDPRLD - Digital Watchdog Preload Value. */
0283 #define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
0284 #define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
0285 #define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0286
0287
0288 /*--------------------TMS570_RTI_WDSTATUS--------------------*/
0289 /* field: DWWD_ST - Windowed Watchdog Status */
0290 #define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5)
0291
0292 /* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
0293 #define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4)
0294
0295 /* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
0296 #define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3)
0297
0298 /* field: KEY_ST - Watchdog key status. */
0299 #define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2)
0300
0301 /* field: DWD_ST - DWD status. */
0302 #define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1)
0303
0304
0305 /*----------------------TMS570_RTI_WDKEY----------------------*/
0306 /* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
0307 #define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
0308 #define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
0309 #define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0310
0311
0312 /*---------------------TMS570_RTI_DWDCNTR---------------------*/
0313 /* field: DWDCNTR - DWD down counter. */
0314 #define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
0315 #define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
0316 #define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
0317
0318
0319 /*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/
0320 /* field: WWDRXN - The DWWD reaction */
0321 #define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
0322 #define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
0323 #define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0324
0325
0326 /*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/
0327 /* field: WWDSIZE - The DWWD window size */
0328 /* Whole 32 bits */
0329
0330 /*------------------TMS570_RTI_INTCLRENABLE------------------*/
0331 /* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
0332 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
0333 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
0334 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0335
0336 /* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
0337 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
0338 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
0339 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0340
0341 /* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
0342 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
0343 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
0344 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0345
0346 /* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
0347 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
0348 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
0349 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0350
0351
0352 /*--------------------TMS570_RTI_COMP0CLR--------------------*/
0353 /* field: CMP0CLR - Compare 0 clear. */
0354 /* Whole 32 bits */
0355
0356 /*--------------------TMS570_RTI_COMP1CLR--------------------*/
0357 /* field: CMP0CLR - Compare 1 clear. */
0358 /* Whole 32 bits */
0359
0360 /*--------------------TMS570_RTI_COMP2CLR--------------------*/
0361 /* field: CMP2CLR - Compare 2 clear. */
0362 /* Whole 32 bits */
0363
0364 /*--------------------TMS570_RTI_COMP3CLR--------------------*/
0365 /* field: CMP3CLR - Compare 3 clear. */
0366 /* Whole 32 bits */
0367
0368
0369 #endif /* LIBBSP_ARM_TMS570_RTI */