bsp/ti_herc/reg_pll.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides PLL interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from PLL.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_PLL
0050 #define LIBBSP_ARM_TMS570_PLL
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t PLLCTL3;           /*PLL Control 3 Register*/
0056   uint8_t reserved1 [108];
0057   uint32_t CLKSLIP;           /*PLL Clock Slip Control Register*/
0058   uint8_t reserved2 [7600];
0059   uint32_t SSWPLL1;           /*PLL Modulation Depth Measurement Control Register*/
0060   uint32_t SSWPLL2;           /*SSW PLL BIST Control Register 2*/
0061   uint32_t SSWPLL3;           /*SSW PLL BIST Control Register 3*/
0062   uint32_t CSDIS;             /*Clock Source Disable Register*/
0063   uint32_t CSDISSET;          /*Clock Source Disable Set Register*/
0064   uint32_t CSDISCLR;          /*Clock Source Disable Clear Register*/
0065   uint8_t reserved3 [24];
0066   uint32_t CSVSTAT;           /*Clock Source Valid Status Register*/
0067   uint8_t reserved4 [24];
0068   uint32_t PLLCTL1;           /*PLL Control 1 Register*/
0069   uint32_t PLLCTL2;           /*PLL Control 2 Register*/
0070   uint8_t reserved5 [16];
0071   uint32_t LPOMONCTL;         /*LPO/Clock Monitor Control Register*/
0072   uint32_t CLKTEST;           /*Clock Test Register*/
0073   uint8_t reserved6 [16];
0074   uint32_t GPREG1;            /*General Purpose Register*/
0075   uint8_t reserved7 [72];
0076   uint32_t GLBSTAT;           /*Global Status Register*/
0077 } tms570_pll_t;
0078
0079
0080 /*---------------------TMS570_PLL_PLLCTL3---------------------*/
0081 /* field: ODPLL2 - Internal PLL Output Divider */
0082 #define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
0083 #define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
0084 #define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
0085
0086 /* field: PLLDIV2 - PLL2 Output Clock Divider */
0087 #define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
0088 #define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
0089 #define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0090
0091 /* field: REFCLKDIV2 - Reference Clock Divider */
0092 #define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
0093 #define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
0094 #define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0095
0096 /* field: PLLMUL2 - PLL2 Multiplication Factor */
0097 #define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
0098 #define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
0099 #define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0100
0101
0102 /*---------------------TMS570_PLL_CLKSLIP---------------------*/
0103 /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
0104 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
0105 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
0106 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
0107
0108 /* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
0109 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
0110 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
0111 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0112
0113
0114 /*---------------------TMS570_PLL_SSWPLL1---------------------*/
0115 /* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
0116 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
0117 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
0118 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0119
0120 /* field: COUNTER_READ_READY - Counter read ready. */
0121 #define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6)
0122
0123 /* field: COUNTER_RESET - Counter reset. */
0124 #define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5)
0125
0126 /* field: COUNTER_EN - Counter enable. */
0127 #define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4)
0128
0129 /* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
0130 #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
0131 #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
0132 #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
0133
0134 /* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
0135 #define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0)
0136
0137
0138 /*---------------------TMS570_PLL_SSWPLL2---------------------*/
0139 /* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
0140 /* Whole 32 bits */
0141
0142 /*---------------------TMS570_PLL_SSWPLL3---------------------*/
0143 /* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
0144 /* Whole 32 bits */
0145
0146 /*----------------------TMS570_PLL_CSDIS----------------------*/
0147 /* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
0148 #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
0149 #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
0150 #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0151
0152 /* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
0153 #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
0154 #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
0155 #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0156
0157
0158 /*--------------------TMS570_PLL_CSDISSET--------------------*/
0159 /* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
0160 #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
0161 #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
0162 #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0163
0164 /* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
0165 #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
0166 #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
0167 #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0168
0169
0170 /*--------------------TMS570_PLL_CSDISCLR--------------------*/
0171 /* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
0172 #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
0173 #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
0174 #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0175
0176 /* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
0177 #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
0178 #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
0179 #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0180
0181
0182 /*---------------------TMS570_PLL_CSVSTAT---------------------*/
0183 /* field: CLKSR_7_3V - Clock source[7-0] valid. */
0184 #define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
0185 #define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
0186 #define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
0187
0188 /* field: CLKSR_1_0V - Clock source[1-0] valid. */
0189 #define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
0190 #define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
0191 #define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0192
0193
0194 /*---------------------TMS570_PLL_PLLCTL1---------------------*/
0195 /* field: ROS - Reset on PLL Slip */
0196 #define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31)
0197
0198 /* field: MASK_SLIP - Mask detection of PLL slip */
0199 #define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
0200 #define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
0201 #define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
0202
0203 /* field: PLLDIV - PLL Output Clock Divider */
0204 #define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
0205 #define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
0206 #define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0207
0208 /* field: ROF - Reset on Oscillator Fail */
0209 #define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23)
0210
0211 /* field: REFCLKDIV - Reference Clock Divider */
0212 #define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
0213 #define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
0214 #define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0215
0216 /* field: PLLMUL - PLL Multiplication Factor */
0217 #define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
0218 #define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
0219 #define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0220
0221
0222 /*---------------------TMS570_PLL_PLLCTL2---------------------*/
0223 /* field: FMENA - Frequency Modulation Enable. */
0224 #define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31)
0225
0226 /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
0227 #define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
0228 #define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
0229 #define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
0230
0231 /* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
0232 #define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
0233 #define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
0234 #define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
0235
0236 /* field: ODPLL - Internal PLL Output Divider. */
0237 #define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
0238 #define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
0239 #define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
0240
0241 /* field: SPR_AMOUNT - Spreading Amount. */
0242 #define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
0243 #define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
0244 #define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0245
0246
0247 /*--------------------TMS570_PLL_LPOMONCTL--------------------*/
0248 /* field: BIAS_ENABLE - Bias enable. */
0249 #define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
0250
0251 /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
0252 #define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
0253
0254 /* field: HFTRIM - High frequency oscillator trim value. */
0255 #define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
0256 #define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
0257 #define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
0258
0259
0260 /*---------------------TMS570_PLL_CLKTEST---------------------*/
0261 /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
0262 #define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
0263
0264 /* field: RANGEDETCTRL - Range detection control. */
0265 #define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
0266
0267 /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
0268 #define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
0269
0270 /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
0271 #define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
0272 #define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
0273 #define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0274
0275
0276 /*---------------------TMS570_PLL_GPREG1---------------------*/
0277 /* field: EMIF_FUNC - Enable EMIF functions to be output. */
0278 #define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31)
0279
0280 /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
0281 #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
0282 #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
0283 #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0284
0285 /* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
0286 #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
0287 #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
0288 #define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
0289
0290 /* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
0291 #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
0292 #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
0293 #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0294
0295
0296 /*---------------------TMS570_PLL_GLBSTAT---------------------*/
0297 /* field: FBSLIP - PLL over cycle slip detection. */
0298 #define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9)
0299
0300 /* field: RFSLIP - PLL under cycle slip detection. */
0301 #define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8)
0302
0303 /* field: OSCFAIL - Oscillator fail flag bit. */
0304 #define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0)
0305
0306
0307
0308 #endif /* LIBBSP_ARM_TMS570_PLL */