bsp/ti_herc/reg_pbist.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides PBIST interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from PBIST.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_PBIST
0050 #define LIBBSP_ARM_TMS570_PBIST
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t DNW[88];           /*Reserved DO NOT WRITE*/
0056   uint32_t RAMT;              /*RAM Configuration Register*/
0057   uint32_t DLR;               /*Datalogger Register*/
0058   uint8_t reserved1 [24];
0059   uint32_t PACT;              /*PBIST Activate/ROM Clock Enable Register*/
0060   uint32_t PBISTID;           /*PBIST ID Register*/
0061   uint32_t OVER;              /*Override Register*/
0062   uint8_t reserved2 [4];
0063   uint32_t FSRF0;             /*Fail Status Fail Register 0*/
0064   uint8_t reserved3 [4];
0065   uint32_t FSRC0;             /*Fail Status Count Register 0*/
0066   uint32_t FSRC1;             /*Fail Status Count Register 1*/
0067   uint32_t FSRA0;             /*Fail Status Address 0 Register*/
0068   uint32_t FSRA1;             /*Fail Status Address 1 Register*/
0069   uint32_t FSRDL0;            /*Fail Status Data Register 0*/
0070   uint8_t reserved4 [4];
0071   uint32_t FSRDL1;            /*Fail Status Data Register 1*/
0072   uint8_t reserved5 [12];
0073   uint32_t ROM;               /*ROM Mask Register*/
0074   uint32_t ALGO;              /*ROM Algorithm Mask Register*/
0075   uint32_t RINFOL;            /*RAM Info Mask Lower Register*/
0076   uint32_t RINFOUL;           /*RAM Info Mask Lower Register*/
0077 } tms570_pbist_t;
0078
0079
0080 /*----------------------TMS570_PBIST_DNW----------------------*/
0081 /* field: Reserved - Do not write */
0082 /* Whole 32 bits */
0083
0084 /*---------------------TMS570_PBIST_RAMT---------------------*/
0085 /* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
0086 #define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
0087 #define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
0088 #define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0089
0090 /* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */
0091 #define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23)
0092 #define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23)
0093 #define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0094
0095 /* field: DWR - Data Width Register */
0096 #define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15)
0097 #define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15)
0098 #define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0099
0100 /* field: SMS - Sense Margin Select Register */
0101 #define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7)
0102 #define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7)
0103 #define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
0104
0105 /* field: PLS - Pipeline Latency Select */
0106 #define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5)
0107 #define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5)
0108 #define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5)
0109
0110 /* field: RLS - RAM Latency Select */
0111 #define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1)
0112 #define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1)
0113 #define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0114
0115
0116 /*----------------------TMS570_PBIST_DLR----------------------*/
0117 /* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
0118 #define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4)
0119
0120 /* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
0121 #define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2)
0122
0123
0124 /*---------------------TMS570_PBIST_PACT---------------------*/
0125 /* field: PACT1 - PBIST Activate */
0126 #define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1)
0127
0128 /* field: PACT0 - ROM Clock Enable Register */
0129 #define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0)
0130
0131
0132 /*--------------------TMS570_PBIST_PBISTID--------------------*/
0133 /* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
0134 #define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
0135 #define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
0136 #define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0137
0138
0139 /*---------------------TMS570_PBIST_OVER---------------------*/
0140 /* field: OVER0 - RINFO Override Bit */
0141 #define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0)
0142
0143
0144 /*---------------------TMS570_PBIST_FSRF0---------------------*/
0145 /* field: FSRF0 - Fail Status 0. */
0146 #define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0)
0147
0148
0149 /*---------------------TMS570_PBIST_FSRC0---------------------*/
0150 /* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
0151 #define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
0152 #define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
0153 #define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0154
0155
0156 /*---------------------TMS570_PBIST_FSRC1---------------------*/
0157 /* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
0158 #define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
0159 #define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
0160 #define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0161
0162
0163 /*---------------------TMS570_PBIST_FSRA0---------------------*/
0164 /* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
0165 #define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
0166 #define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
0167 #define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0168
0169
0170 /*---------------------TMS570_PBIST_FSRA1---------------------*/
0171 /* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
0172 #define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
0173 #define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
0174 #define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0175
0176
0177 /*--------------------TMS570_PBIST_FSRDL0--------------------*/
0178 /* field: FSRDL1 - Failure data on port 1 */
0179 /* Whole 32 bits */
0180
0181 /*--------------------TMS570_PBIST_FSRDL1--------------------*/
0182 /* field: FSRDL1 - Failure data on port 1 */
0183 /* Whole 32 bits */
0184
0185 /*----------------------TMS570_PBIST_ROM----------------------*/
0186 /* field: ROM - ROM Mask */
0187 #define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
0188 #define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
0189 #define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0190
0191
0192 /*---------------------TMS570_PBIST_ALGO---------------------*/
0193 /* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
0194 /* Whole 32 bits */
0195
0196 /*--------------------TMS570_PBIST_RINFOL--------------------*/
0197 /* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
0198 /* Whole 32 bits */
0199
0200 /*--------------------TMS570_PBIST_RINFOUL--------------------*/
0201 /* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
0202 /* Whole 32 bits */
0203
0204
0205 #endif /* LIBBSP_ARM_TMS570_PBIST */