bsp/ti_herc/reg_htu.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides HTU interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from HTU.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_HTU
0050 #define LIBBSP_ARM_TMS570_HTU
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t GC;                /*Global Control Register*/
0056   uint32_t CPENA;             /*Control Packet Enable Register*/
0057   uint32_t BUSY0;             /*Control Packet Busy Register 0*/
0058   uint32_t BUSY1;             /*Control Packet Busy Register 1*/
0059   uint32_t BUSY2;             /*Control Packet Busy Register 2*/
0060   uint32_t BUSY3;             /*Control Packet Busy Register 3*/
0061   uint32_t ACPE;              /*Active Control Packet and Error Register*/
0062   uint8_t reserved1 [4];
0063   uint32_t RLBECTRL;          /*Request Lost and Bus Error Control Register*/
0064   uint32_t BFINTS;            /*Buffer Full Interrupt Enable Set Register*/
0065   uint32_t BFINTC;            /*Buffer Full Interrupt Enable Clear Register*/
0066   uint8_t reserved2 [8];
0067   uint32_t INTOFF0;           /*Interrupt Offset Register 0*/
0068   uint32_t INTOFF1;           /*Interrupt Offset Register 1*/
0069   uint32_t BIM;               /*Buffer Initialization Mode Register*/
0070   uint32_t RLOSTFL;           /*Request Lost Flag Register*/
0071   uint32_t BFINTFL;           /*Buffer Full Interrupt Flag Register*/
0072   uint32_t BERINTFL;          /*BER Interrupt Flag Register*/
0073   uint32_t MP1S;              /*Memory Protection 1 Start Address Register*/
0074   uint32_t MP1E;              /*Memory Protection 1 End Address Register*/
0075   uint32_t DCTRL;             /*Debug Control Register*/
0076   uint32_t WPR;               /*Watch Point Register*/
0077   uint32_t WMR;               /*Watch Mask Register*/
0078   uint32_t ID;                /*Module Identification Register*/
0079   uint32_t PCR;               /*Parity Control Register*/
0080   uint32_t PAR;               /*Parity Address Register*/
0081   uint8_t reserved3 [4];
0082   uint32_t MPCS;              /*Memory Protection Control and Status Register*/
0083   uint32_t MP0S;              /*Memory Protection 0 Start Address Register*/
0084   uint32_t MP0E;              /*Memory Protection 0 End Address Register*/
0085 } tms570_htu_t;
0086
0087
0088 /*-----------------------TMS570_HTU_GC-----------------------*/
0089 /* field: VBUSHOLD - Hold the VBUS bus */
0090 #define TMS570_HTU_GC_VBUSHOLD BSP_BIT32(24)
0091
0092 /* field: HTUEN - Transfer Unit Enable Bit */
0093 #define TMS570_HTU_GC_HTUEN BSP_BIT32(16)
0094
0095 /* field: DEBM - Debug Mode */
0096 #define TMS570_HTU_GC_DEBM BSP_BIT32(8)
0097
0098 /* field: HTURES - HTU Software Reset Request */
0099 #define TMS570_HTU_GC_HTURES BSP_BIT32(0)
0100
0101
0102 /*----------------------TMS570_HTU_CPENA----------------------*/
0103 /* field: CPENA - CP Enable Bits */
0104 #define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
0105 #define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0106 #define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0107
0108
0109 /*----------------------TMS570_HTU_BUSY0----------------------*/
0110 /* field: BUSY0A - Busy Flag for CP A of DCP 0 */
0111 #define TMS570_HTU_BUSY0_BUSY0A BSP_BIT32(24)
0112
0113 /* field: BUSY0B - Busy Flag for CP B of DCP 0 */
0114 #define TMS570_HTU_BUSY0_BUSY0B BSP_BIT32(16)
0115
0116 /* field: BUSY1A - Busy Flag for CP A of DCP 1 */
0117 #define TMS570_HTU_BUSY0_BUSY1A BSP_BIT32(8)
0118
0119 /* field: BUSY1B - Busy Flag for CP B of DCP 1 */
0120 #define TMS570_HTU_BUSY0_BUSY1B BSP_BIT32(0)
0121
0122
0123 /*----------------------TMS570_HTU_BUSY1----------------------*/
0124 /* field: BUSY2A - Busy Flag for CP A of DCP 2 */
0125 #define TMS570_HTU_BUSY1_BUSY2A BSP_BIT32(24)
0126
0127 /* field: BUSY2B - Busy Flag for CP B of DCP 2 */
0128 #define TMS570_HTU_BUSY1_BUSY2B BSP_BIT32(16)
0129
0130 /* field: BUSY3A - Busy Flag for CP A of DCP 3 */
0131 #define TMS570_HTU_BUSY1_BUSY3A BSP_BIT32(8)
0132
0133 /* field: BUSY3B - Busy Flag for CP B of DCP 3 */
0134 #define TMS570_HTU_BUSY1_BUSY3B BSP_BIT32(0)
0135
0136
0137 /*----------------------TMS570_HTU_BUSY2----------------------*/
0138 /* field: BUSY4A - Busy Flag for CP A of DCP 4 */
0139 #define TMS570_HTU_BUSY2_BUSY4A BSP_BIT32(24)
0140
0141 /* field: BUSY4B - Busy Flag for CP B of DCP 4 */
0142 #define TMS570_HTU_BUSY2_BUSY4B BSP_BIT32(16)
0143
0144 /* field: BUSY5A - Busy Flag for CP A of DCP 5 */
0145 #define TMS570_HTU_BUSY2_BUSY5A BSP_BIT32(8)
0146
0147 /* field: BUSY5B - Busy Flag for CP B of DCP 5 */
0148 #define TMS570_HTU_BUSY2_BUSY5B BSP_BIT32(0)
0149
0150
0151 /*----------------------TMS570_HTU_BUSY3----------------------*/
0152 /* field: BUSY6A - Busy Flag for CP A of DCP 6 */
0153 #define TMS570_HTU_BUSY3_BUSY6A BSP_BIT32(24)
0154
0155 /* field: BUSY6B - Busy Flag for CP B of DCP 6 */
0156 #define TMS570_HTU_BUSY3_BUSY6B BSP_BIT32(16)
0157
0158 /* field: BUSY7A - Busy Flag for CP A of DCP 7 */
0159 #define TMS570_HTU_BUSY3_BUSY7A BSP_BIT32(8)
0160
0161 /* field: BUSY7B - Busy Flag for CP B of DCP 7 */
0162 #define TMS570_HTU_BUSY3_BUSY7B BSP_BIT32(0)
0163
0164
0165 /*----------------------TMS570_HTU_ACPE----------------------*/
0166 /* field: ERRF - Error Flag */
0167 #define TMS570_HTU_ACPE_ERRF BSP_BIT32(31)
0168
0169
0170 /*--------------------TMS570_HTU_RLBECTRL--------------------*/
0171 /* field: BERINTENA - Bus Error Interrupt Enable Bit */
0172 #define TMS570_HTU_RLBECTRL_BERINTENA BSP_BIT32(16)
0173
0174 /* field: CORL - Continue On Request Lost Error */
0175 #define TMS570_HTU_RLBECTRL_CORL BSP_BIT32(8)
0176
0177 /* field: RLINTENA - Request Lost Interrupt Enable Bit */
0178 #define TMS570_HTU_RLBECTRL_RLINTENA BSP_BIT32(0)
0179
0180
0181 /*---------------------TMS570_HTU_BFINTS---------------------*/
0182 /* field: BFINTENA - Bus Full Interrupt Enable Bits. */
0183 #define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
0184 #define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0185 #define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0186
0187
0188 /*---------------------TMS570_HTU_BFINTC---------------------*/
0189 /* field: BFINTDIS -  */
0190 #define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
0191 #define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0192 #define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0193
0194
0195 /*---------------------TMS570_HTU_INTOFF0---------------------*/
0196 /* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
0197 #define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
0198 #define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
0199 #define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0200
0201 /* field: CPOFF0 - CP Offset. */
0202 #define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4)
0203 #define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4)
0204 #define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0205
0206
0207 /*---------------------TMS570_HTU_INTOFF1---------------------*/
0208 /* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
0209 #define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
0210 #define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
0211 #define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0212
0213 /* field: CPOFF1 - CP Offset. */
0214 #define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4)
0215 #define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4)
0216 #define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0217
0218
0219 /*-----------------------TMS570_HTU_BIM-----------------------*/
0220 /* field: BIM - Buffer Initialization Mode */
0221 #define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
0222 #define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
0223 #define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0224
0225
0226 /*---------------------TMS570_HTU_RLOSTFL---------------------*/
0227 /* field: CPRLFL - CP Request Lost Flags */
0228 #define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
0229 #define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
0230 #define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0231
0232
0233 /*---------------------TMS570_HTU_BFINTFL---------------------*/
0234 /* field: BFINTFL - Buffer Full Interrupt Flags */
0235 #define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
0236 #define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
0237 #define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0238
0239
0240 /*--------------------TMS570_HTU_BERINTFL--------------------*/
0241 /* field: BERINTFL - Bus Error Interrupt Flags */
0242 #define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
0243 #define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
0244 #define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0245
0246
0247 /*----------------------TMS570_HTU_MP1S----------------------*/
0248 /* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
0249 /* Whole 32 bits */
0250
0251 /*----------------------TMS570_HTU_MP1E----------------------*/
0252 /* field: ENDADDRESS1 - The end address defines at which address the region ends. */
0253 /* Whole 32 bits */
0254
0255 /*----------------------TMS570_HTU_DCTRL----------------------*/
0256 /* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
0257 #define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
0258 #define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
0259 #define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0260
0261 /* field: HTUDBGS - HTU Debug Status. */
0262 #define TMS570_HTU_DCTRL_HTUDBGS BSP_BIT32(16)
0263
0264 /* field: DBREN - Debug Request Enable */
0265 #define TMS570_HTU_DCTRL_DBREN BSP_BIT32(0)
0266
0267
0268 /*-----------------------TMS570_HTU_WPR-----------------------*/
0269 /* field: WP - Watch Point Register */
0270 /* Whole 32 bits */
0271
0272 /*-----------------------TMS570_HTU_WMR-----------------------*/
0273 /* field: WM - Watch Mask Register */
0274 /* Whole 32 bits */
0275
0276 /*-----------------------TMS570_HTU_ID-----------------------*/
0277 /* field: CLASS - Module Class */
0278 #define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
0279 #define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
0280 #define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0281
0282 /* field: TYPE - Subtype within a Class */
0283 #define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15)
0284 #define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
0285 #define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0286
0287 /* field: REV - Module Revision Number */
0288 #define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7)
0289 #define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7)
0290 #define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0291
0292
0293 /*-----------------------TMS570_HTU_PCR-----------------------*/
0294 /* field: COPE - Continue on Parity Error */
0295 #define TMS570_HTU_PCR_COPE BSP_BIT32(16)
0296
0297 /* field: TEST - Test. */
0298 #define TMS570_HTU_PCR_TEST BSP_BIT32(8)
0299
0300 /* field: PARITY_ENA - Enable/Disable Parity Checking. */
0301 #define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
0302 #define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0303 #define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0304
0305
0306 /*-----------------------TMS570_HTU_PAR-----------------------*/
0307 /* field: PEFT - Parity Error Fault Flag. */
0308 #define TMS570_HTU_PAR_PEFT BSP_BIT32(16)
0309
0310 /* field: PAOFF - PAOFF */
0311 #define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
0312 #define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8)
0313 #define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0314
0315
0316 /*----------------------TMS570_HTU_MPCS----------------------*/
0317 /* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
0318 #define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
0319 #define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
0320 #define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
0321
0322 /* field: MPEFT1 - MPEFT1 */
0323 #define TMS570_HTU_MPCS_MPEFT1 BSP_BIT32(17)
0324
0325 /* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
0326 #define TMS570_HTU_MPCS_MPEFT0 BSP_BIT32(16)
0327
0328 /* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
0329 #define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
0330 #define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11)
0331 #define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0332
0333
0334 /*----------------------TMS570_HTU_MP0S----------------------*/
0335 /* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
0336 /* Whole 32 bits */
0337
0338 /*----------------------TMS570_HTU_MP0E----------------------*/
0339 /* field: ENDADDRESS0 - The end address defines at which address the region ends. */
0340 /* Whole 32 bits */
0341
0342
0343 #endif /* LIBBSP_ARM_TMS570_HTU */